https://docs.amd.com/r/en-US/pg055-axi-bridge-pcie/Root-Port-Status/Control-Register-Offset-0x148?contentId=G097Vb642iCWrns8y2P0GA
Root Port Status/Control Register (Offset 0x148) - Root Port Status/Control Register (Offset 0x148)...
The Root Port Status/Control register provides access to Root Port specific status and control. This register is only implemented for Root Port cores. For...
port statusrootcontrolregisteroffset