https://docs.amd.com/r/en-US/pg381-perf-axi-tg-spec/ARREQ_COUNTER-Register-0x2018?contentId=2ifZhWXrmB9WLmQXym~MXg
ARREQ_COUNTER Register (0x2018) - ARREQ_COUNTER Register (0x2018) - 1.0 English - PG381
Table 1. ARREQ_COUNTER Register (0x2018) Bit Default Value Access Type Description 31:0 0x0000_0000 RO Number of Read requests issued by the TG
counterregisterenglish