https://docs.amd.com/r/en-US/pg381-perf-axi-tg-spec/AXI_VLD_RDY_STATS-Register-0x21B0?contentId=xGEpOyjORHg1fxh0H4F~6A
AXI_VLD_RDY_STATS Register (0x21B0) - AXI_VLD_RDY_STATS Register (0x21B0) - 1.0 English - PG381
Table 1. AXI_VLD_RDY_STATS Register (0x21B0) Bit Default Value Access Type Description 31:10 0 RO Reserved 9 0 RO Current status of awvalid signal. This...
axivldrdystatsregister