https://docs.amd.com/r/en-US/pg381-perf-axi-tg-spec/PLAY_PAUSE-Register-0x401C?contentId=gcvGlygXfNnvB~KyGaGajw
PLAY_PAUSE Register (0x401C) - PLAY_PAUSE Register (0x401C) - 1.0 English - PG381
Table 1. PLAY_PAUSE Register (0x401C) Bit Default Value Access Type Description 31:1 0x0000_0001 R/W Reserved 0 1 R/W Write 0 to pause the traffic and write 1...
play pauseregisterenglish