https://community.altera.com/discussions/fpga-device/undesired-sidebands-on-cyclone-iv-e-pll-output/163430
undesired sidebands on Cyclone IV E PLL output | Altera Community - 163430
I am using a PLL in a Cyclone IV E. I have a 20 MHz oscillator connected to a clock-input pin. I am trying to get 200 MHz as the output. For the design, I... -...
cyclone iv e