https://ez.analog.com/rf/wide-band-rf-transceivers/design-support-adrv9001-adrv9007/f/q-a/577912/adrv900x-xilinx-interface-ip---cutout-tdd-functionality-ip-documentation
ADRV900x Xilinx interface IP - cutout TDD functionality / IP documentation - Q&A - Support ADRV9001...
We have been using the ADI ADRV900x interface IP block with a Xilinx FPGA without problem. However, our application does not use TDD mode and I see that a large
interface ip