https://blog.vmsplice.net/2026/01/building-virtio-serial-fpga-device-part_04001134.html
Stefan Hajnoczi: Building a virtio-serial FPGA device (Part 5): UART receiver and transmitter
This is the fifth post in a series about building a virtio-serial device in Verilog for an FPGA development board. This time we
https://vmsplice.net/
Stefan Hajnoczi
stefan