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https://docs.amd.com/r/en-US/pg051-tri-mode-eth-mac/Frame-Reception-with-Errors Frame Reception with Errors - Frame Reception with Errors - 9.0 English - PG051 The following figure illustrates an unsuccessful frame reception (for example, a fragment frame or a frame with an incorrect FCS). In this case, the... frame reception errors english https://docs.amd.com/r/en-US/pg051-tri-mode-eth-mac/Physical-Sublayers-PCS-PMA-and-PMD?contentId=nUIRX~D0DgB~NBDQtuZbXw Physical Sublayers PCS, PMA, and PMD - Physical Sublayers PCS, PMA, and PMD - 9.0 English - PG051 The combination of the Physical Coding Sublayer (PCS), Physical Medium Attachment (PMA), and Physical Medium Dependent (PMD) sublayer constitute the physical... physical pcs pma pmd english https://docs.amd.com/r/en-US/pg051-tri-mode-eth-mac/Transmitter-Interface?contentId=4M5h~xnzcWxl8sB~5o23Ug Transmitter Interface - Transmitter Interface - 9.0 English - PG051 Transmit Interface AXI4-Stream Signal Pins defines the AXI4-Stream transmit signals of the core, which are used to transmit data from the user to the core.... transmitter interface english https://docs.amd.com/r/en-US/pg051-tri-mode-eth-mac/Statistics-Reset?contentId=OWWegI9zhT0PvU4~XjXOug Statistics Reset - Statistics Reset - 9.0 English - PG051 When the Statistics Counters are included, it is possible to include logic to ensure the counters are cleared to zero upon a hardware reset. Without this logic... statistics reset english https://docs.amd.com/r/en-US/pg051-tri-mode-eth-mac/VLAN-Tagged-Frames?contentId=HuOp6dIn0KSWe3kEhR9tlg VLAN Tagged Frames - VLAN Tagged Frames - 9.0 English - PG051 Transmission of a VLAN tagged frame (if enabled) can be seen in the following figure . The handshaking signals across the interface do not change. However, the... vlan tagged frames english https://docs.amd.com/r/en-US/pg051-tri-mode-eth-mac/Port-Changes-from-v7.0-to-v8.0?contentId=YdAYzWTZU2eaTz11ES~VmQ Port Changes from v7.0 to v8.0 - Port Changes from v7.0 to v8.0 - 9.0 English - PG051 port changes english https://docs.amd.com/r/en-US/pg051-tri-mode-eth-mac/MDIO-Configuration-and-Control?contentId=HC9pG1axL6qm2dgDTbYIFw MDIO Configuration and Control - MDIO Configuration and Control - 9.0 English - PG051 Access to the MDIO interface through the management interface is entirely register mapped. To perform an MDIO write, the write data must first be written to... configuration control english https://docs.amd.com/r/en-US/pg051-tri-mode-eth-mac/Shared-Logic?contentId=VH8Ag53v2Ymg4OsLEeUiVw Shared Logic - Shared Logic - 9.0 English - PG051 As part of the hierarchical changes to the core that were implemented in v8.0, it is now possible for an instance of the core to include logic that can be... shared logic english https://docs.amd.com/r/en-US/pg051-tri-mode-eth-mac/1-Gbps-Ethernet-MAC-Core-Interfaces?contentId=kvC6yUSqtbt7YmfSCBBxPA 1 Gbps Ethernet MAC Core Interfaces - 1 Gbps Ethernet MAC Core Interfaces - 9.0 English - PG051 The core supplied for 1 Gbps operation provides either a GMII or RGMII interface. These are typically used to connect the MAC to an external PHY device. The... ethernet mac core interfaces english https://docs.amd.com/r/en-US/pg051-tri-mode-eth-mac/AXI4-Lite-Signal-Definition?contentId=v26~pkxFvt_o0tMkYYO5jA AXI4-Lite Signal Definition - AXI4-Lite Signal Definition - 9.0 English - PG051 The following table describes the optional signals that you used to access the Ethernet MAC core level, including configuration, status, and MDIO access. See... lite signal definition english https://docs.amd.com/r/en-US/pg051-tri-mode-eth-mac/Port-Changes-from-v8.0-to-v8.1?contentId=~Ce_1cNcIPHP9Bnw9iAsjg Port Changes from v8.0 to v8.1 - Port Changes from v8.0 to v8.1 - 9.0 English - PG051 port changes english https://docs.amd.com/r/en-US/pg051-tri-mode-eth-mac/Destination-Address Destination Address - Destination Address - 9.0 English - PG051 This MAC Address field is the first field of the Ethernet frame that is always provided in the packet data for transmissions and is always retained in the... destination address english https://docs.amd.com/r/en-US/pg051-tri-mode-eth-mac/Reference-Boards?contentId=4AlUwju2adW6_LnS_9NxMA Reference Boards - Reference Boards - 9.0 English - PG051 reference boards english https://docs.amd.com/r/en-US/pg051-tri-mode-eth-mac/AVB-Endpoint AVB Endpoint - AVB Endpoint - 9.0 English - PG051 When enabling AVB Endpoint operation, disable flow control and jumbo mode and use only in full-duplex mode. Note: The AVB Endpoint is only available if the... avb endpoint english https://docs.amd.com/r/en-US/pg051-tri-mode-eth-mac/Using-the-AVB-Specific-Frame-Filters?contentId=3~gHCmf0ICW5c~xMfVNniw Using the AVB Specific Frame Filters - Using the AVB Specific Frame Filters - 9.0 English - PG051 This section is only applicable if the TEMAC solution is implemented with the optional Ethernet AVB Endpoint functionality. The three AVB frame filters are... using avb specific frame filters https://docs.amd.com/r/en-US/pg051-tri-mode-eth-mac/TX-Arbiter?contentId=uuYq4FcEGKBRVrpH32d~tA TX Arbiter - TX Arbiter - 9.0 English - PG051 tx arbiter english https://docs.amd.com/r/en-US/pg051-tri-mode-eth-mac/Flow-Control-Basics Flow Control Basics - Flow Control Basics - 9.0 English - PG051 A MAC can transmit a Pause Control frame to request that its link partner cease transmission for a specific period of time. For example, the left MAC in the... flow control basics english https://docs.amd.com/r/en-US/pg051-tri-mode-eth-mac/GMII-Transmitter-Interface?contentId=_C6s1FrqXbq69J0XMB6vNA GMII Transmitter Interface - GMII Transmitter Interface - 9.0 English - PG051 The logic required to implement the GMII transmitter logic is illustrated in the following figure. The gtx_clk is a user-supplied 125 MHz reference clock... transmitter interface english https://docs.amd.com/r/en-US/pg051-tri-mode-eth-mac/Board?contentId=k_h7BykGQaYRAONnO99WYw Board - Board - 9.0 English - PG051 This tab, shown in the following figure, only appears if a supported board has been pre-selected as the project part. In the Associate IP Interface table, only... board english https://docs.amd.com/r/en-US/pg051-tri-mode-eth-mac/Receiver-Logic?contentId=vf~Kdm6lF4r3x1DD_Spdhg Receiver Logic - Receiver Logic - 9.0 English - PG051 In this implementation, the input clock is used for sampling the RGMII RX signal at the device IOBs. This creates placement constraints: a clock capable input... receiver logic english https://docs.amd.com/r/en-US/pg051-tri-mode-eth-mac/Resource-Utilization Resource Utilization - Resource Utilization - 9.0 English - PG051 For full details about performance and resource utilization, visit the Performance and Resource Utilization web page. resource utilization english https://docs.amd.com/r/en-US/pg051-tri-mode-eth-mac/Frame-Filter Frame Filter - Frame Filter - 9.0 English - PG051 When the frame filter is selected with no management interface, only a subset of its functionality is available. Because there is no user access to internal... frame filter english https://docs.amd.com/r/en-US/pg051-tri-mode-eth-mac/Keep-it-Registered?contentId=SG6KOOEnzXhGXmHNmFAzjA Keep it Registered - Keep it Registered - 9.0 English - PG051 To simplify timing and increase system performance in an FPGA, keep all inputs and outputs registered between your application and the core. This means that... keep it registered english https://docs.amd.com/r/en-US/pg051-tri-mode-eth-mac/10-100-1000-Mbps-Ethernet-FIFO?contentId=MF3n_olqo8NkBZwfIo3fZQ 10, 100, 1000 Mbps Ethernet FIFO - 10, 100, 1000 Mbps Ethernet FIFO - 9.0 English - PG051 The 10, 100, and 1000 Mbps Ethernet FIFO is available for MAC data rates of up to 1 Gbps. It is described in the following files:... mbps ethernet fifo english https://docs.amd.com/r/en-US/pg051-tri-mode-eth-mac/Other-Changes-from-v7.0-to-v8.0?contentId=08cmHYOzFrcg3fxBC9TevA Other Changes from v7.0 to v8.0 - Other Changes from v7.0 to v8.0 - 9.0 English - PG051 other changes english https://docs.amd.com/r/en-US/pg051-tri-mode-eth-mac/MDIO-Bus-System?contentId=Zhu1nFN0IkzaK~Xkc4CEfw MDIO Bus System - MDIO Bus System - 9.0 English - PG051 The Management Data Input/Output (MDIO) interface for access to Ethernet PHY devices for 1 Gbps operation and slower speeds is defined in IEEE 802.3, clause... bus system english https://docs.amd.com/r/en-US/pg051-tri-mode-eth-mac/RX-Legacy-Traffic-Interface?contentId=f_t3KVx2zbC2elbGbso8Qw RX Legacy Traffic Interface - RX Legacy Traffic Interface - 9.0 English - PG051 The signals forming the RX Legacy Traffic Interface are defined in Table 1. The timing of this interface is as described in the Receiving Inbound Frames, with... rx legacy traffic interface english https://docs.amd.com/r/en-US/pg051-tri-mode-eth-mac/User-Interfaces User Interfaces - User Interfaces - 9.0 English - PG051 user interfaces english