Robuta

https://docs.amd.com/r/en-US/pg210-25g-ethernet/STAT_HARD_RSFEC_RX_DELAY_REG-04A4?contentId=vVJX9bcKl9Ph~mt22HufNw STAT_HARD_RSFEC_RX_DELAY_REG: 04A4 - STAT_HARD_RSFEC_RX_DELAY_REG: 04A4 - 5.1 English - PG210 Table 1. STAT_HARD_RSFEC_RX_DELAY_REG: 04A4 Bits Default Type Signal 10 0 RO stat_hard_rsfec_rx_delay This register indicates the HARD_RFSEC_RX_DELAY value, it... stathardrxdelay https://docs.amd.com/r/en-US/pg210-25g-ethernet/STAT_FEC_INC_CORRECT_COUNT_MSB-0924 STAT_FEC_INC_CORRECT_COUNT_MSB: 0924 - STAT_FEC_INC_CORRECT_COUNT_MSB: 0924 - 5.1 English - PG210 Table 1. STAT_FEC_INC_CORRECT_COUNT_MSB: 0924 Bits Default Type Signal 15:0 0 HIST stat_fec_inc_correct_count_count[47:32] statfecinccorrectcount https://docs.amd.com/r/en-US/pg210-25g-ethernet/Duplex-Mode-of-Operation Duplex Mode of Operation - Duplex Mode of Operation - 5.1 English - PG210 In this mode of operation, both the transmitter and receiver of the core are active and loopback functionality is provided at the GT output interface, that is,... mode of operationduplexenglish https://docs.amd.com/r/3.3-English/pg210-25g-ethernet/Common-Clock/Reset-Signals Common Clock/Reset Signals - Common Clock/Reset Signals - 3.3 English - PG210 Table 1. Common Clock/Reset Signals Name Size I/O Description sys_reset 1 I Reset for core. Note: This port is available when the Include GT subcore in core... commonclockresetsignalsenglish https://docs.amd.com/r/en-US/pg210-25g-ethernet/Receive-AXI4-Stream-Interface?contentId=d4yoDj0Au0W7kw4t~841yg Receive AXI4-Stream Interface - Receive AXI4-Stream Interface - 5.1 English - PG210 Receive AXI4-Stream Interface shows the two AXI4-Stream Interfaces, for express (rx_axis_e_*) and preempt traffic (rx_axis_p_*), when the core is generated... receivestreaminterfaceenglish https://docs.amd.com/r/3.3-English/pg210-25g-ethernet/STAT_RX_RSFEC_STATUS_REG-043C STAT_RX_RSFEC_STATUS_REG: 043C - STAT_RX_RSFEC_STATUS_REG: 043C - 3.3 English - PG210 Table 1. STAT_RX_RSFEC_STATUS_REG: 043C Bits Default Type Signal 0 1 RO LL stat_rx_rsfec_lane_alignment_status 1 1 RO LL stat_rx_rsfec_hi_ser statrxregenglish https://docs.amd.com/r/en-US/pg210-25g-ethernet/Frame-Lock-State-Machine Frame Lock State Machine - Frame Lock State Machine - 5.1 English - PG210 The frame lock state machine searches for the frame marker, consisting of 16 consecutive 1s followed by 16 consecutive 0s. This functionality is fully... frame lockstate machineenglish https://docs.amd.com/r/en-US/pg210-25g-ethernet/References References - References - 5.1 English - PG210 These documents provide supplemental material useful with this product guide: 25/50G Gigabit Ethernet Consortium Schedule 3 (v1.6) (25/50G Ethernet... referencesenglish https://docs.amd.com/r/en-US/pg210-25g-ethernet/STAT_LT_STATUS_REG1-0464?contentId=PKa7YfZZJZ5jZSC05NO~Jw STAT_LT_STATUS_REG1: 0464 - STAT_LT_STATUS_REG1: 0464 - 5.1 English - PG210 Table 1. STAT_LT_STATUS_REG1: 0464 Bits Default Type Signal 0 0 RO stat_lt_initialize_from_rx 16 0 RO stat_lt_preset_from_rx statltenglish https://docs.amd.com/r/3.3-English/pg210-25g-ethernet/TICK_REG-0020?contentId=wPaizE3Hbyi90lQ~eCgCFg TICK_REG: 0020 - TICK_REG: 0020 - 3.3 English - PG210 Table 1. TICK_REG: 0020 Bits Default Type Signal 0 0 WO tick_reg This is a clear on write register. tickregenglish https://docs.amd.com/r/en-US/pg210-25g-ethernet/STAT_RX_PACKET_64_BYTES_LSB-0828 STAT_RX_PACKET_64_BYTES_LSB: 0828 - STAT_RX_PACKET_64_BYTES_LSB: 0828 - 5.1 English - PG210 Table 1. STAT_RX_PACKET_64_BYTES_LSB: 0828 Bits Default Type Signal 31:0 0 HIST stat_rx_packet_64_bytes_count[31:0] statrxpacketbytes https://docs.amd.com/r/en-US/pg210-25g-ethernet/Changes-from-v2.1-to-v2.2 Changes from v2.1 to v2.2 - Changes from v2.1 to v2.2 - 5.1 English - PG210 changesenglish https://docs.amd.com/r/3.3-English/pg210-25g-ethernet/Changes-from-v2.2-to-v2.3?contentId=sWwUr1RvTZyCVlYOw1cT0g Changes from v2.2 to v2.3 - Changes from v2.2 to v2.3 - 3.3 English - PG210 changesenglish https://docs.amd.com/r/3.3-English/pg210-25g-ethernet/STAT_RX_TOOLONG_MSB-08B4 STAT_RX_TOOLONG_MSB: 08B4 - STAT_RX_TOOLONG_MSB: 08B4 - 3.3 English - PG210 Table 1. STAT_RX_TOOLONG_MSB: 08B4 Bits Default Type Signal 15:0 0 HIST stat_rx_toolong_count[47:32] statrxmsbenglish https://docs.amd.com/r/en-US/pg210-25g-ethernet/STAT_RX_MULTICAST_LSB-08E0 STAT_RX_MULTICAST_LSB: 08E0 - STAT_RX_MULTICAST_LSB: 08E0 - 5.1 English - PG210 Table 1. STAT_RX_MULTICAST_LSB: 08E0 Bits Default Type Signal 31:0 0 HIST stat_rx_multicast_count[31:0] statrxmulticastlsbenglish https://docs.amd.com/r/en-US/pg210-25g-ethernet/STAT_RX_OVERSIZE_MSB-08AC?contentId=NJwH~lUTy0gXeL5pv~zI~w STAT_RX_OVERSIZE_MSB: 08AC - STAT_RX_OVERSIZE_MSB: 08AC - 5.1 English - PG210 Table 1. STAT_RX_OVERSIZE_MSB: 08AC Bits Default Type Signal 15:0 0 HIST stat_rx_oversize_count[47:32] statrxoversizemsbenglish https://docs.amd.com/r/3.3-English/pg210-25g-ethernet/VERSAL_CHANNEL_NUM_REG-0x014C?contentId=CzfYXFJ8pw3gb~uXkSimag VERSAL_CHANNEL_NUM_REG: 0x014C - VERSAL_CHANNEL_NUM_REG: 0x014C - 3.3 English - PG210 Table 1. VERSAL_CHANNEL_NUM_REG: 0x014C Bits Default Type Signal 1:0 2'b0 RW ctl_gtye5_chan_num versalchannelnumregenglish https://docs.amd.com/r/en-US/pg210-25g-ethernet/STAT_TX_PACKET_64_BYTES_MSB-0724 STAT_TX_PACKET_64_BYTES_MSB: 0724 - STAT_TX_PACKET_64_BYTES_MSB: 0724 - 5.1 English - PG210 Table 1. STAT_TX_PACKET_64_BYTES_MSB: 0724 Bits Default Type Signal 15:0 0 HIST stat_tx_packet_64_bytes_count[47:32] stattxpacketbytes https://docs.amd.com/r/en-US/pg210-25g-ethernet/XGMII/25GMII-Interface-Ports?contentId=Sx8er_gMfe9wMZL_nUgG1g XGMII/25GMII Interface Ports - XGMII/25GMII Interface Ports - 5.1 English - PG210 The following table shows the XGMII/25GMII I/O ports. Table 1. XGMII/25GMII Interface Ports Name I/O Clock Domain Description rx_mii_d[63:0] O rx_mii_clk... interfaceportsenglish https://docs.amd.com/r/en-US/pg210-25g-ethernet/Signal-Integrity Signal Integrity - Signal Integrity - 5.1 English - PG210 When bringing up a board for the first time and the 10G/25G Ethernet Subsystem does not seem to be achieving word sync, the most likely problem is related to... signal integrityenglish https://docs.amd.com/r/3.3-English/pg210-25g-ethernet/Answer-Records?contentId=rQAxxCCCtdoZJzDSqbEuxg Answer Records - Answer Records - 3.3 English - PG210 Answer Records include information about commonly encountered problems, helpful information on how to resolve these problems, and any known issues with a... answer recordsenglish https://boopstcpages.neocities.org/SHOWCASE/pg210 showcase pg210 showcase https://docs.amd.com/r/en-US/pg210-25g-ethernet/STAT_TX_UNICAST_MSB-07D4 STAT_TX_UNICAST_MSB: 07D4 - STAT_TX_UNICAST_MSB: 07D4 - 5.1 English - PG210 Table 1. STAT_TX_UNICAST_MSB: 07D4 Bits Default Type Signal 15:0 0 HIST stat_tx_unicast_count[47:32] stattxmsbenglish https://docs.amd.com/r/3.3-English/pg210-25g-ethernet/CONFIGURATION_LT_PRESET_REG-0108 CONFIGURATION_LT_PRESET_REG: 0108 - CONFIGURATION_LT_PRESET_REG: 0108 - 3.3 English - PG210 Table 1. CONFIGURATION_LT_PRESET_REG: 0108 Bits Default Type Signal 0 0 RW ctl_lt_preset_to_tx configurationltpresetregenglish https://docs.amd.com/r/en-US/pg210-25g-ethernet/STAT_TX_BROADCAST_MSB-07E4 STAT_TX_BROADCAST_MSB: 07E4 - STAT_TX_BROADCAST_MSB: 07E4 - 5.1 English - PG210 Table 1. STAT_TX_BROADCAST_MSB: 07E4 Bits Default Type Signal 15:0 0 HIST stat_tx_broadcast_count[47:32] stattxbroadcastmsbenglish https://docs.amd.com/r/3.3-English/pg210-25g-ethernet/STAT_RX_PACKET_LARGE_LSB-0888 STAT_RX_PACKET_LARGE_LSB: 0888 - STAT_RX_PACKET_LARGE_LSB: 0888 - 3.3 English - PG210 Table 1. STAT_RX_PACKET_LARGE_LSB: 0888 Bits Default Type Signal 31:0 0 HIST stat_rx_packet_large_count[31:0] statrxpacketlargelsb https://docs.amd.com/r/3.3-English/pg210-25g-ethernet/STAT_RX_STOMPED_FCS_MSB-08D4 STAT_RX_STOMPED_FCS_MSB: 08D4 - STAT_RX_STOMPED_FCS_MSB: 08D4 - 3.3 English - PG210 Table 1. STAT_RX_STOMPED_FCS_MSB: 08D4 Bits Default Type Signal 15:0 0 HIST stat_rx_stomped_fcs_count[47:32] statrxstompedfcsmsb https://docs.amd.com/r/en-US/pg210-25g-ethernet/Debugging Debugging - Debugging - 5.1 English - PG210 This appendix includes details about resources available on the AMD Support website and debugging tools. Tip: If the IP generation halts with an error, there... debuggingenglish https://docs.amd.com/r/en-US/pg210-25g-ethernet/STAT_RX_RSFEC_STATUS_REG-043C?contentId=BGdMIuN6H_5pvgaPJaxtSA STAT_RX_RSFEC_STATUS_REG: 043C - STAT_RX_RSFEC_STATUS_REG: 043C - 5.1 English - PG210 Table 1. STAT_RX_RSFEC_STATUS_REG: 043C Bits Default Type Signal 0 1 RO LL stat_rx_rsfec_lane_alignment_status 1 0 RO LH stat_rx_rsfec_hi_ser statrxregenglish https://docs.amd.com/r/en-US/pg210-25g-ethernet/RS-FEC-Support RS-FEC Support - RS-FEC Support - 5.1 English - PG210 rsfecsupportenglish https://docs.amd.com/r/3.3-English/pg210-25g-ethernet/Duplex-Mode-of-Operation?contentId=QauYqApgZnZQRxt1gusdng Duplex Mode of Operation - Duplex Mode of Operation - 3.3 English - PG210 In this mode of operation, both the transmitter and receiver of the core are active and loopback functionality is provided at the GT output interface, that is,... mode of operationduplexenglish https://docs.amd.com/r/en-US/pg210-25g-ethernet/Output-Generation Output Generation - Output Generation - 5.1 English - PG210 For details, see the Vivado Design Suite User Guide: Designing with IP (UG896). outputgenerationenglish https://docs.amd.com/r/en-US/pg210-25g-ethernet/Support-for-IEEE-Standard-1588v2 Support for IEEE Standard 1588v2 - Support for IEEE Standard 1588v2 - 5.1 English - PG210 support forieeestandardenglish https://docs.amd.com/r/3.3-English/pg210-25g-ethernet/References?contentId=uGhTye8RxjfYj5f90irmNg References - References - 3.3 English - PG210 These documents provide supplemental material useful with this product guide: 25/50G Gigabit Ethernet Consortium Schedule 3 (v1.6) (http://25gethernet.org/)... referencesenglish https://docs.amd.com/r/3.3-English/pg210-25g-ethernet/Performance-and-Resource-Utilization Performance and Resource Utilization - Performance and Resource Utilization - 3.3 English - PG210 For full details about performance and resource utilization, visit the Performance and Resource Utilization web page . resource utilizationperformanceenglish