Robuta

https://docs.amd.com/r/en-US/pg232-mipi-csi2-rx/Protocol-Description?contentId=9qDfalt0FF0LrcaHBb9bFw Protocol Description - Protocol Description - 6.0 English - PG232 protocoldescriptionenglish https://docs.amd.com/r/5.4-English/pg232-mipi-csi2-rx/Clock-Frequencies?contentId=gcQwZkJbr39Mj6GTgTe3rA Clock Frequencies - Clock Frequencies - 5.4 English - PG232 clockfrequenciesenglish https://docs.amd.com/r/5.2-English/pg232-mipi-csi2-rx/Lane-n-Information-Registers?contentId=8XOddv8tcVzewJTMlknhpA Lanen Information Registers - Lanen Information Registers - 5.2 English - PG232 informationregistersenglish https://docs.amd.com/r/en-US/pg232-mipi-csi2-rx/Video-Format-Bridge-VFB-Latency?contentId=1lfcX1MqAO15jkjZ1DHcCQ Video Format Bridge (VFB) Latency - Video Format Bridge (VFB) Latency - 6.0 English - PG232 The VFB core latency is the time from the VFB input stream interface tvalid to VFB output stream interface tvalid. The following table provides the latency... video formatbridgevfblatencyenglish https://docs.amd.com/r/en-US/pg232-mipi-csi2-rx/Required-Constraints?contentId=qIyrZQ09aydY0p6eBg5c~A Required Constraints - Required Constraints - 6.0 English - PG232 The XDC constraints are delivered when the subsystem is generated. requiredconstraintsenglish https://docs.amd.com/r/5.4-English/pg232-mipi-csi2-rx/AXI-Crossbar AXI Crossbar - AXI Crossbar - 5.4 English - PG232 The AXI Crossbar core or SmartConnect core (for Versal adaptive SoC) is used in the subsystem to route AXI4-Lite requests to corresponding sub-cores based on... axicrossbarenglish https://docs.amd.com/r/5.1-English/pg232-mipi-csi2-rx/ZCU102-Setup-Details?contentId=9JnWSXACZGJ0a2BA3qMfQg ZCU102 Setup Details - ZCU102 Setup Details - 5.1 English - PG232 This section lists the prerequisites and setup required for ZCU102 based application example design. setupdetailsenglish https://docs.amd.com/r/5.2-English/pg232-mipi-csi2-rx/Example-1?contentId=KcWfhXuncqcXbRPF9PlFaQ Example 1 - Example 1 - 5.2 English - PG232 When RAW12 and RAW8 are transferred with two pixels per clock, the data port width of the video_out interface is 24-bits. Within the 24-bits the RAW8 pixels... exampleenglish https://docs.amd.com/r/5.1-English/pg232-mipi-csi2-rx/Designing-with-the-Subsystem?contentId=jrKpPiDoFuvAXwyVF_h2tQ Designing with the Subsystem - Designing with the Subsystem - 5.1 English - PG232 This chapter includes guidelines and additional information to facilitate designing with the subsystem. designingsubsystemenglish https://docs.amd.com/r/en-US/pg232-mipi-csi2-rx/I/O-Planning?contentId=B_HLtkNzwn8gmPLJdQ5DSQ I/O Planning - I/O Planning - 6.0 English - PG232 The MIPI CSI-2 RX Subsystem provides an I/O planner feature for I/O selection. In the Pin Assignment tab, dedicated byte clocks (DBC) or quad byte clocks (QBC)... planningenglish https://docs.amd.com/r/en-US/pg232-mipi-csi2-rx/Video-Format-Bridge-VFB-Latency Video Format Bridge (VFB) Latency - Video Format Bridge (VFB) Latency - 6.0 English - PG232 The VFB core latency is the time from the VFB input stream interface tvalid to VFB output stream interface tvalid. The following table provides the latency... video formatbridgevfblatencyenglish https://docs.amd.com/r/en-US/pg232-mipi-csi2-rx/Applications?contentId=xxQW6EngGOqccgBDPHt3Aw Applications - Applications - 6.0 English - PG232 The AMD MIPI CSI-2 RX controller implements a Camera Serial Interface between a camera sensor and a programmable device performing baseband processing. The... applicationsenglish https://docs.amd.com/r/5.2-English/pg232-mipi-csi2-rx/Clock-Lane-Information-Register?contentId=GiEmzMMM9GD9rOwzRxp0sA Clock Lane Information Register - Clock Lane Information Register - 5.2 English - PG232 The Clock Lane Information register is described in Table: Clock Lane Information Register (0x3C) . The Stop state is captured in this register. Table 2-29:... clocklaneinformationregisterenglish https://docs.amd.com/r/5.2-English/pg232-mipi-csi2-rx/Protocol-Configuration-Register?contentId=hl~hp0WSiTtn_7CFpfcjLQ Protocol Configuration Register - Protocol Configuration Register - 5.2 English - PG232 The Protocol Configuration register is described in Table: Protocol Configuration Register (0x04) and allows you to configure protocol specific options such as... protocolconfigurationregisterenglish https://docs.amd.com/r/en-US/pg232-mipi-csi2-rx/Transceiver-Placement?contentId=mcxwgJMxbDdFEZMfhiA4GQ Transceiver Placement - Transceiver Placement - 6.0 English - PG232 This section is not applicable for this subsystem. transceiverplacementenglish https://docs.amd.com/r/5.1-English/pg232-mipi-csi2-rx/MIPI-CSI-2-RX-Controller?contentId=JL_bkN91MCSGa1I1qZ8dSA MIPI CSI-2 RX Controller - MIPI CSI-2 RX Controller - 5.1 English - PG232 The MIPI CSI-2 RX Controller core consists of multiple layers defined in the MIPI CSI-2 RX, such as the lane management layer, low level protocol and byte to... mipi csirxcontrollerenglish https://docs.amd.com/r/5.2-English/pg232-mipi-csi2-rx/MIPI-CSI-2-RX-Controller MIPI CSI-2 RX Controller - MIPI CSI-2 RX Controller - 5.2 English - PG232 The MIPI CSI-2 RX Controller core consists of multiple layers defined in the MIPI CSI-2 RX, such as the lane management layer, low level protocol and byte to... mipi csirxcontrollerenglish https://docs.amd.com/r/en-US/pg232-mipi-csi2-rx/Core-Overview?contentId=zP4~QfK2fFbZ~I1E6YPmsw Core Overview - Core Overview - 6.0 English - PG232 The MIPI CSI-2 RX subsystem allows you to quickly create systems based on the MIPI protocol. It interfaces between MIPI-based image sensors and an image sensor... core overviewenglish https://docs.amd.com/r/en-US/pg232-mipi-csi2-rx/Please-Read-Important-Legal-Notices?contentId=IW5CphtJMXZb2pQ_M_u6nw Please Read: Important Legal Notices - Please Read: Important Legal Notices - 6.0 English - PG232 The information presented in this document is for informational purposes only and may contain technical inaccuracies, omissions, and typographical errors. The... important legal noticesplease readenglish https://docs.amd.com/r/5.2-English/pg232-mipi-csi2-rx/Implementing-the-Example-Design?contentId=Dy7xaV8WvNAaeeCbb5E0NQ Implementing the Example Design - Implementing the Example Design - 5.2 English - PG232 Note: The figures in this chapter are illustrations of the Vivado Integrated Design Environment (IDE). The layout depicted here might vary from the current... the exampleimplementingdesignenglish https://docs.amd.com/r/5.1-English/pg232-mipi-csi2-rx/References References - References - 5.1 English - PG232 These documents provide supplemental material useful with this product guide: 1. MIPI Alliance Standard for Camera Serial Interface CSI-2:... referencesenglish https://docs.amd.com/r/en-US/pg232-mipi-csi2-rx/Banking?contentId=jZ~3cm92Edskp6fJ2B5Rhw Banking - Banking - 6.0 English - PG232 The MIPI CSI-2 RX Subsystem MIPI D-PHY sub-core provides a Pin Assignment tab in the Vivado IDE to select the HP I/O bank. The clock lane and data lane(s) are... bankingenglish https://docs.amd.com/r/en-US/pg232-mipi-csi2-rx/Unsupported-Features?contentId=4RdLCoxHQ9wqKxV2BxnUKA Unsupported Features - Unsupported Features - 6.0 English - PG232 Some YUV Data Types (YUV 420 (10-bit)) are not supported when the Video Format Bridge is included. Dynamic line rate is not supported. Escape mode processing... unsupported featuresenglish https://docs.amd.com/r/en-US/pg232-mipi-csi2-rx/Sub-Core-Details?contentId=Y24OHQDI4QjCAI4DUbHAwg Sub-Core Details - Sub-Core Details - 6.0 English - PG232 core detailssubenglish https://docs.amd.com/r/5.2-English/pg232-mipi-csi2-rx/Application-Example-Design Application Example Design - Application Example Design - 5.2 English - PG232 This chapter contains step-by-step instructions for generating an MIPI CSI-2 RX Subsystem application example design from the MIPI CSI-2 RX Subsystem by using... application exampledesignenglish https://docs.amd.com/r/en-US/pg232-mipi-csi2-rx/I/O-Standard-and-Placement?contentId=SHL9nwr9W2RPfATqmg9uHQ I/O Standard and Placement - I/O Standard and Placement - 6.0 English - PG232 MIPI standard serial I/O ports should use MIPI_DPHY_DCI for the I/O standard in the XDC file for the UltraScale+ family. The LOC and I/O standards must be... standardplacementenglish https://docs.amd.com/r/en-US/pg232-mipi-csi2-rx/Pixel-Packing-for-RAW8-Data-Type?contentId=jN_a4hgz5NrVvvNQTTss3Q Pixel Packing for RAW8 Data Type - Pixel Packing for RAW8 Data Type - 6.0 English - PG232 Table 1. Pixel Packing for RAW8 Data Type Bit Position 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RAW8 s7 s6 s5 s4... data typepixelpackingenglish https://docs.amd.com/r/5.2-English/pg232-mipi-csi2-rx/Configuration-Tab Configuration Tab - Configuration Tab - 5.2 English - PG232 The Configuration tab page provides core related configuration parameters. The subsystem configuration screen is shown in This Figure . Figure 4-2: Subsystem... configurationtabenglish