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https://docs.amd.com/r/en-US/pg278-v-frmbuf/Master-Answer-Record-for-the-Core?contentId=mpheu9a0oWbd3lyfT39JKw Master Answer Record for the Core - Master Answer Record for the Core - 3.0 English - PG278 Master Answer Record for the Video Frame Buffer Read AR: 68764 Master Answer Record for the Video Frame Buffer Write AR: 68765 for the master answer record core https://docs.amd.com/r/2.4-English/pg278-v-frmbuf/YUVX12?contentId=fvUOWORYCU15qtXrAcYLrA YUVX12 - YUVX12 - 2.4 English - PG278 Packed YUV 4:4:4, 12 bits per component. Every YUV 4:4:4 pixel in memory is represented with 40 bits, as shown. Bits [39:36] do not contain pixel information.... english https://docs.amd.com/r/2.4-English/pg278-v-frmbuf/YUV16?contentId=k~FGtLEE7KyitHmsd9NVVQ YUV16 - YUV16 - 2.4 English - PG278 Packed YUV 4:4:4, 16 bits per component. Every YUV 4:4:4 pixel in memory is represented with 48 bits, as shown. 47:32 31:16 15:0 V U Y english https://docs.amd.com/r/en-US/pg278-v-frmbuf/RGBA8 RGBA8 - RGBA8 - 3.0 English - PG278 Packed RGB with alpha, eight bits per component. Every RGB with an alpha pixel is represented with 32 bits, as shown. Bits[31:24] contain alpha information,... english https://docs.amd.com/r/2.4-English/pg278-v-frmbuf/General-Design-Guidelines?contentId=OszKY5Tw2xDSKQRgpBz3hQ General Design Guidelines - General Design Guidelines - 2.4 English - PG278 This section compares the differences between Video Frame Buffer Read and Video Frame Buffer Write IPs to the AXI Video Direct Memory Access IP core. The AXI... general design guidelines english https://docs.amd.com/r/2.4-English/pg278-v-frmbuf/Resets?contentId=K21xFNo3tXFAlGTB4ifv1w Resets - Resets - 2.4 English - PG278 The Video Frame Buffer Read and Video Frame Buffer Write IPs have only a hardware reset option, ap_rst_n pin. No software reset option is available. The... resets english https://docs.amd.com/r/en-US/pg278-v-frmbuf/BGR8?contentId=NMGIwt7h5Y5PLDJCPLCMWQ BGR8 - BGR8 - 3.0 English - PG278 Packed BGR, eight bits per component. Every RGB pixel in memory is represented with 24 bits, as shown. The images need to be stored in memory in raster order,... english https://docs.amd.com/r/en-US/pg278-v-frmbuf/Changes-from-v2.2-to-v2.3?contentId=RnjCJfr7rHzneN8en22phg Changes from v2.2 to v2.3 - Changes from v2.2 to v2.3 - 3.0 English - PG278 Video Frame Buffer v2.3 is a direct replacement for v2.2. V2.3 supports two new features, that is, 16K resolution and Y_U_V8, that is, a three Planar video... changes english https://docs.amd.com/r/2.4-English/pg278-v-frmbuf/RGBX10 RGBX10 - RGBX10 - 2.4 English - PG278 Packed RGB, 10 bits per component. Every RGB pixel is represented with 32 bits, as shown. Bits[31:30] do not contain any pixel information. 31:30 29:20 19:10... english https://docs.amd.com/r/2.4-English/pg278-v-frmbuf/Height-0x0018-Register Height (0x0018) Register - Height (0x0018) Register - 2.4 English - PG278 The Height register encodes the number of active scan lines per frame (or per field for interlaced video). Supported values are between 64 and the value... height register english https://docs.amd.com/r/2.4-English/pg278-v-frmbuf/RGBA8?contentId=3KPwM81lzXrPznOxoPqmBA RGBA8 - RGBA8 - 2.4 English - PG278 Packed RGB with alpha, 8 bits per component. Every RGB with alpha pixel is represented with 32 bits, as shown. Bits[31:24] contain alpha information, 0 is... english https://docs.amd.com/r/en-US/pg278-v-frmbuf/Clocking?contentId=H~2VwdWU8q~~jU~q_oglhA Clocking - Clocking - 3.0 English - PG278 The Video Frame Buffer Read and Video Frame Buffer Write IPs have a single clock domain. All interfaces (master and slave AXI4-Stream video interfaces, the... clocking english https://docs.amd.com/r/en-US/pg278-v-frmbuf/System-Considerations System Considerations - System Considerations - 3.0 English - PG278 The Video Frame Buffer read and write IPs must be configured for the actual input and output image frame size to operate properly. The IP can be connected to... system considerations english https://docs.amd.com/r/en-US/pg278-v-frmbuf/Synthesis-and-Implementation?contentId=KTTSdVZR6uPVn9tH0M2jvg Synthesis and Implementation - Synthesis and Implementation - 3.0 English - PG278 For details about synthesis and implementation, see the Vivado Design Suite User Guide: Designing with IP (UG896). synthesis implementation english https://docs.amd.com/r/en-US/pg278-v-frmbuf/UYVY8 UYVY8 - UYVY8 - 3.0 English - PG278 Packed YUV 4:2:2, 8 bits per component. Every two YUV 4:2:2 pixels in memory are represented with 32 bits, as shown. 31:24 23:16 15:8 7:0 Y1 V0 Y0 U0 english https://docs.amd.com/r/2.4-English/pg278-v-frmbuf/Memory-Mapped-AXI4-Interface Memory Mapped AXI4 Interface - Memory Mapped AXI4 Interface - 2.4 English - PG278 The memory mapped AXI4 interface runs on the ap_clk clock domain. The signals follow the specification as defined in the Vivado Design Suite: AXI Reference... memory mapped interface english https://docs.amd.com/r/2.4-English/pg278-v-frmbuf/IP-Interrupt-Enable-0x0008-Register IP Interrupt Enable (0x0008) Register - IP Interrupt Enable (0x0008) Register - 2.4 English - PG278 This register allows interrupts to be enabled selectively. Currently, two interrupt sources are available, ap_done and ap_ready . ap_done is triggered after... ip interrupt enable register english https://docs.amd.com/r/2.4-English/pg278-v-frmbuf/Width-0x0010-Register Width (0x0010) Register - Width (0x0010) Register - 2.4 English - PG278 The Width register encodes the number of Active Pixels per Scanline. Supported values are between 64 and the value provided in the Maximum Number of Columns... width register english https://docs.amd.com/r/2.4-English/pg278-v-frmbuf/Overview?contentId=QjwMGmzIi~0glNWYSwSCnw Overview - Overview - 2.4 English - PG278 Many video applications require frame buffers to handle frame rate changes or changes to the image dimensions (scaling or cropping). The Video Frame Buffer... overview english