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https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/Errors Errors - Errors - 2.0 English - PG344 errors english https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/QDMA_VF_MAILBOX-0x5000?contentId=p7WZPMcBTp0T75yBNURb6Q QDMA_VF_MAILBOX (0x5000) - QDMA_VF_MAILBOX (0x5000) - 2.0 English - PG344 Table 1. QDMA_VF_MAILBOX (0x05000) Register Space Registers (Address) Address Description Function Status Register (0x5000) 0x5000 Status register bits... qdma vf mailbox english https://docs.amd.com/r/1.0-English/pg344-pcie-dma-versal/Unsupported-Request Unsupported Request - Unsupported Request - 1.0 English - PG344 A device for PCIe might not be capable of satisfying a specific read request. For example, if the read request targets an unsupported address for PCIe, the... unsupported request english https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/User-Interrupts?contentId=q2FTHlgYlDGhA95y3SBUHA User Interrupts - User Interrupts - 2.0 English - PG344 The user logic must hold usr_irq_req active-High even after receiving usr_irq_ack (acks) to keep the interrupt pending register asserted. This enables the... user interrupts english https://docs.amd.com/r/1.0-English/pg344-pcie-dma-versal/MSI-X-Interrupts?contentId=vk2O_rhIMJvrpRkZEKClrg MSI-X Interrupts - MSI-X Interrupts - 1.0 English - PG344 The DMA supports up to 32 different interrupt source for MSI-X, which consists of a maximum of 16 usable DMA interrupt vectors and a maximum of 16 usable user... msi x interrupts english https://docs.amd.com/r/1.0-English/pg344-pcie-dma-versal/C2H_COMPLETION_DATA_3-0x03C C2H_COMPLETION_DATA_3 (0x03C) - C2H_COMPLETION_DATA_3 (0x03C) - 1.0 English - PG344 Table 1. C2H_COMPLETION_DATA_3 (0x03C) Bit Default Access Type Field Description [31:0] 0 NA AXI-ST C2H Completion Data [127:96] completion data english https://docs.amd.com/r/1.0-English/pg344-pcie-dma-versal/PCIe-BARs-Tab?contentId=XsGOSJ7CxQXlA8NrU0BNHA PCIe BARs Tab - PCIe BARs Tab - 1.0 English - PG344 The PCIe BARs tab is shown in the following figure. Figure 1. PCIe BARs Tab Base Address Register Overview In Endpoint configuration, the core supports up to... pcie bars tab english https://docs.amd.com/r/1.0-English/pg344-pcie-dma-versal/PCIe-DMA-Tab?contentId=gB_RBpJ_FjiMRrxUmZZ92w PCIe DMA Tab - PCIe DMA Tab - 1.0 English - PG344 The PCIe DMA tab is shown in the following figure. Figure 1. PCIe DMA Tab Number of DMA Read Channels Available selection is from 1 to 4. Number of DMA Write... pcie dma tab english https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/Design-Flow-Steps?contentId=xI_QEgnE1w7Ei6rvno8vZg Design Flow Steps - Design Flow Steps - 2.0 English - PG344 This section describes customizing and generating the subsystem, constraining the subsystem, and the simulation, synthesis, and implementation steps that are... design flow steps english https://docs.amd.com/r/1.0-English/pg344-pcie-dma-versal/C2H-Stream-Engine?contentId=tTBJWFrt986zSGOekAaY9g C2H Stream Engine - C2H Stream Engine - 1.0 English - PG344 The C2H Stream Engine DMA writes the stream packets to the host memory into the descriptor provided by the host driver through the C2H descriptor queue. The... stream engine english https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/DMA-Register-space DMA Register space - DMA Register space - 2.0 English - PG344 DMA queue space registers can be accessed through the AXI4-Lite Slave interface. QDMA Queue space PF register addresses and QDMA Queue space VF register... dma register space english https://docs.amd.com/r/1.0-English/pg344-pcie-dma-versal/Port-Descriptions Port Descriptions - Port Descriptions - 1.0 English - PG344 Note: The Versal ACAP DMA and Bridge Subsystem for PCIe IP is implemented in a modular IP architecture. This means that GTs, PCIe IP, and the subsystem IP are... port descriptions english https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/Host-Profile?contentId=5clmlnnixBGDUMO6M42B1Q Host Profile - Host Profile - 2.0 English - PG344 Host profile must be programmed to represent root port host. Host profile can be programmed through context programming. Select QDMA_CTXT_SELC_HOST_PROFILE... host profile english https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/AXI-MM-Transfer-For-H2C?contentId=BQr~Ov5sgM2yE4EUJsdWXg AXI-MM Transfer For H2C - AXI-MM Transfer For H2C - 2.0 English - PG344 The following figure shows a basic flow chart that explains the data transfer for H2C. The flow chart color coding is as follows: Green is the application... axi mm transfer english https://docs.amd.com/r/1.0-English/pg344-pcie-dma-versal/QDMA-Subsystem-Limitations?contentId=Pz7fVO5TH_HOfssZyjdoSg QDMA Subsystem Limitations - QDMA Subsystem Limitations - 1.0 English - PG344 The limitations of the QDMA are as follows: The DMA supports a maximum of 256 Queues on any VF function. Slave Bridge AXI does not support Narrow Burst... qdma subsystem limitations english https://docs.amd.com/r/1.0-English/pg344-pcie-dma-versal/H2C-Stream-Data-Aligner?contentId=3Ibly1K4uh1B9AnVKugRmQ H2C Stream Data Aligner - H2C Stream Data Aligner - 1.0 English - PG344 The H2C engine has a data aligner that aligns the data to zero Bytes (0B) boundary before issuing it to the user logic. This allows the start address of a... stream data aligner english https://docs.amd.com/r/1.0-English/pg344-pcie-dma-versal/Implementation-Design-Overview?contentId=m1F7XB3F7mQHtSe4z_MGQQ Implementation Design Overview - Implementation Design Overview - 1.0 English - PG344 For implementation design, the AXI Block RAM controller can be used as a scratch pad memory to write and read to Block RAM locations. design overview implementation english https://docs.amd.com/r/1.0-English/pg344-pcie-dma-versal/IRQ-Block-User-Vector-Number-0x84?contentId=bsuVsFcpog8DI8UQbSd9uA IRQ Block User Vector Number (0x84) - IRQ Block User Vector Number (0x84) - 1.0 English - PG344 If MSI is enabled, this register specifies the MSI or MSI-X vector number of the MSI. In legacy interrupts, only the 2 LSB of each field should be used to map... block user irq vector number english https://docs.amd.com/r/1.0-English/pg344-pcie-dma-versal/RTL-Version-Register-0x22414 RTL Version Register (0x22414) - RTL Version Register (0x22414) - 1.0 English - PG344 Table 1. RTL Version Register (0x22414) Bit Default Access Type Field Description [31:16] 0x1fd3 RO QDMA ID [15:0] 0 RO Vivado versions 0x10: Vivado version... rtl version register english https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/GT-Quad-Locations GT Quad Locations - GT Quad Locations - 2.0 English - PG344 The following table identifies the GT Quad(s) that can be used for each PCIe controller location. The Quad shown in bold is the most adjacent GT Quad for each... gt quad locations english https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/MSI-X-Interrupts?contentId=YlsDit~2uczC2_LAOFiJDA MSI-X Interrupts - MSI-X Interrupts - 2.0 English - PG344 The DMA supports up to 32 different interrupt source for MSI-X, which consists of a maximum of 16 usable DMA interrupt vectors and a maximum of 16 usable user... msi x interrupts english https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/Documentation Documentation - Documentation - 2.0 English - PG344 This product guide is the main document associated with the subsystem. This guide, along with documentation related to all products that aid in the design... documentation english https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/C2H-Channel-Control-0x08?contentId=Uc0blOkjth2_TmlOXeECMg C2H Channel Control (0x08) - C2H Channel Control (0x08) - 2.0 English - PG344 Table 1. C2H Channel Control (0x08) Bit Index Default Access Type Description W1S Control Bit descriptions are the same as in C2H Channel Control (0x04). channel control english https://docs.amd.com/r/1.0-English/pg344-pcie-dma-versal/AXI4-Stream-Status-Ports?contentId=Ze1~SqG~027i8tk2znvxZw AXI4-Stream Status Ports - AXI4-Stream Status Ports - 1.0 English - PG344 Table 1. AXI-ST C2H Status Port Descriptions Port Name I/O Description axis_c2h_status_valid O Valid per descriptor. axis_c2h_status_qid [10:0] O QID of the... stream status ports english https://docs.amd.com/r/1.0-English/pg344-pcie-dma-versal/XDMA-Subsystem?contentId=T4LTEyyRk63bCNxuY8BwQw XDMA Subsystem - XDMA Subsystem - 1.0 English - PG344 Four host-to-card (H2C/Read) data channels Four card-to-host (C2H/Write) data channels Per channel descriptor bypass for custom descriptor creation... subsystem english https://docs.amd.com/r/1.0-English/pg344-pcie-dma-versal/Modular-IP-Architecture?contentId=ENfnaJhBzOa_mmr2MLQhEA Modular IP Architecture - Modular IP Architecture - 1.0 English - PG344 The XDMA Subsystem is packaged in what is called a modular IP architecture. Modular IP architecture refers to the programmable logic integrated block for PCIe... modular ip architecture english https://docs.amd.com/r/1.0-English/pg344-pcie-dma-versal/Errors?contentId=E7H2NJeD0aMfYraHuRXgWw Errors - Errors - 1.0 English - PG344 errors english https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/Application-Software-Development?contentId=ikJy3HsX0CmxPXqH00KUyQ Application Software Development - Application Software Development - 2.0 English - PG344 This section provides details about the Linux device driver that is provided with the core. application software development english https://docs.amd.com/r/1.0-English/pg344-pcie-dma-versal/QDMA-PF-Address-Register-Space QDMA PF Address Register Space - QDMA PF Address Register Space - 1.0 English - PG344 All the physical function (PF) registers are listed in the qdma_v4_0_pf_registers.csv available in the Register Reference File. Tip: When you generate the IP... qdma pf address register space https://docs.amd.com/r/1.0-English/pg344-pcie-dma-versal/PCIe-Block-Interface?contentId=H8B36pvITsZybntnGXmrdg PCIe Block Interface - PCIe Block Interface - 1.0 English - PG344 pcie block interface english https://docs.amd.com/r/1.0-English/pg344-pcie-dma-versal/AXI4-Memory-Mapped-C2H-Flow?contentId=WfbURc6YkgeW2AGqCiQwLQ AXI4 Memory Mapped C2H Flow - AXI4 Memory Mapped C2H Flow - 1.0 English - PG344 Figure 1. AXI4 Memory Mapped Card to Host (C2H) Flow Diagram memory mapped flow english https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/AXI4-Stream-C2H-Flow?contentId=Qcwq1m6lOzW9KhbnoLMp_Q AXI4-Stream C2H Flow - AXI4-Stream C2H Flow - 2.0 English - PG344 Figure 1. AXI4-Stream C2H Flow Diagram stream flow english https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/Expansion-ROM?contentId=VyRlA5KlQygcODrErVLFLQ Expansion ROM - Expansion ROM - 2.0 English - PG344 If selected, the Expansion ROM is activated and can be a value from 2 KB to 4 GB. According to the PCI Local Bus Specification ( PCI-SIG Specifications... expansion rom english https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/Port-Descriptions Port Descriptions - Port Descriptions - 2.0 English - PG344 Note: The AMD Versal adaptive SoC DMA and Bridge Subsystem for PCIe IP is implemented in a modular IP architecture. This means that GTs, PCIe IP, and the... port descriptions english https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/QDMA-Subsystem-Limitations QDMA Subsystem Limitations - QDMA Subsystem Limitations - 2.0 English - PG344 The limitations of the QDMA are as follows: The DMA supports a maximum of 256 Queues on any VF function. Slave Bridge AXI does not support Narrow Burst... qdma subsystem limitations english https://docs.amd.com/r/1.0-English/pg344-pcie-dma-versal/XDMA-Operations?contentId=aHWf8KYNJ6O3lqZzfY7R9w XDMA Operations - XDMA Operations - 1.0 English - PG344 operations english https://docs.amd.com/r/1.0-English/pg344-pcie-dma-versal/IRQ-Block-User-Vector-Number-0x88 IRQ Block User Vector Number (0x88) - IRQ Block User Vector Number (0x88) - 1.0 English - PG344 If MSI is enabled, this register specifies the MSI or MSI-X vector number of the MSI. In legacy interrupts only the 2 LSB of each field should be used to map... block user irq vector number english https://docs.amd.com/r/1.0-English/pg344-pcie-dma-versal/USER_INTERRUPT-0x094?contentId=8_4M5MsryX6iD5x1LGigaw USER_INTERRUPT (0x094) - USER_INTERRUPT (0x094) - 1.0 English - PG344 Table 1. User Interrupt (0x094) Bit Default Access Type Field Description [31:20] 0 NA Reserved [19:12] 0 RW usr_irq_in_fun User interrupt function number... user interrupt english https://docs.amd.com/r/1.0-English/pg344-pcie-dma-versal/Port-ID?contentId=l4dcSfFZ~w0O3yK6g4uu1g Port ID - Port ID - 1.0 English - PG344 Port ID is the categorization of some queues on the FPGA side. When the DMA is shared by more than one user application, the port ID provides indirection to... port id english https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/Output-Logging?contentId=TNNBXhOL4OrJKHYzDrNumQ Output Logging - Output Logging - 2.0 English - PG344 The simulation process creates three output log files. They are tx.dat, rx.dat, and error.dat. The rx.dat and tx.dat files each contain a detailed record of... output logging english https://docs.amd.com/r/1.0-English/pg344-pcie-dma-versal/Verilog-Flow?contentId=IOOK5cwV~pu9Td9zbOKCqg Verilog Flow - Verilog Flow - 1.0 English - PG344 The model provides a mechanism for outputting the simulation waveform to a file using the +dump_all command line parameter. verilog flow english https://docs.amd.com/r/1.0-English/pg344-pcie-dma-versal/C2H_COMPLETION_DATA_3-0x03C?contentId=qLncTVs8MM4ah9B8axFtzw C2H_COMPLETION_DATA_3 (0x03C) - C2H_COMPLETION_DATA_3 (0x03C) - 1.0 English - PG344 Table 1. C2H_COMPLETION_DATA_3 (0x03C) Bit Default Access Type Field Description [31:0] 0 NA AXI-ST C2H Completion Data [127:96] completion data english https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/BDF-Table?contentId=0qoywK2D7mjq4mvtyqL_TA BDF Table - BDF Table - 2.0 English - PG344 Address translations for AXI address is done based on BDF table programming (0x2420 to 0x2434). These BDF table entries can be programmed through the AXI Slave... bdf table english https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/QDMA-Global-Ports?contentId=HgVHj2VNkaEFRWfYXfL5HQ QDMA Global Ports - QDMA Global Ports - 2.0 English - PG344 Table 1. QDMA Global Port Descriptions Port Name I/O Description sys_clk I Should be driven by the ODIV2 port of reference clock IBUFDS_GTE4. See the Versal... global ports qdma english https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/IRQ-Block-User-Vector-Number-0x8C?contentId=DrgD0Gis9vj8JVS1yN3O4w IRQ Block User Vector Number (0x8C) - IRQ Block User Vector Number (0x8C) - 2.0 English - PG344 If MSI is enabled, this register specifies the MSI or MSI-X vector number of the MSI. In legacy interrupts only the 2 LSB of each field should be used to map... block user irq vector number english https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/Completion-Timer?contentId=8~eWs4coctIiNxuG~1nYxw Completion Timer - Completion Timer - 2.0 English - PG344 The Completion Timer engine supports the timer trigger mode in the Completion context. It supports 2048 queues, and each queue has its own timer. When the... completion timer english https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/Legacy-Interrupt?contentId=wamgRMEALhEDnbxHGiDriQ Legacy Interrupt - Legacy Interrupt - 2.0 English - PG344 The QDMA supports the legacy interrupt for physical function, and it is expected that the single queue will be associated with interrupt. To enable the legacy... legacy interrupt english https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/Address-Alignment Address Alignment - Address Alignment - 2.0 English - PG344 Table 1. Address Alignment Interface Type Datapath Width Address Restriction AXI4 MM 64, 128, 256, 512 None AXI4-Stream 64, 128, 256, 512 None AXI4 MM fixed... address alignment english https://docs.amd.com/r/1.0-English/pg344-pcie-dma-versal/Interrupt-Module?contentId=jyoU33Xo4rmVoT2JMr1WCQ Interrupt Module - Interrupt Module - 1.0 English - PG344 The IRQ module aggregates interrupts from various sources. The interrupt sources are queue-based interrupts, user interrupts and error interrupts. Queue-based... interrupt module english https://docs.amd.com/r/1.0-English/pg344-pcie-dma-versal/C2H-Channel-Control-0x04?contentId=Gbu9G_2S4Zu0Dp1V2nV7sQ C2H Channel Control (0x04) - C2H Channel Control (0x04) - 1.0 English - PG344 Table 1. C2H Channel Control (0x04) Bit Index Default Access Type Description 31:28 Reserved 27 0x0 RW Disables the metadata writeback for C2H AXI4-Stream. No... channel control english https://docs.amd.com/r/1.0-English/pg344-pcie-dma-versal/Interrupt-Flow?contentId=hrZT4OD9xqB4mixcm7hLjw Interrupt Flow - Interrupt Flow - 1.0 English - PG344 Figure 1. Interrupt Flow interrupt flow english https://docs.amd.com/r/1.0-English/pg344-pcie-dma-versal/Unsupported-Request?contentId=a_hyBndx3cNMti7ni8L3vA Unsupported Request - Unsupported Request - 1.0 English - PG344 A device for PCIe might not be capable of satisfying a specific read request. For example, if the read request targets an unsupported address for PCIe, the... unsupported request english https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/Error-Interrupt Error Interrupt - Error Interrupt - 2.0 English - PG344 There are Leaf Error Aggregators in different places. They log the errors and propagate the errors to the Central Error Aggregator. Each Leaf Error Aggregator... error interrupt english https://docs.amd.com/r/1.0-English/pg344-pcie-dma-versal/QDMA_TRQ_MSIX_VF-0x4000?contentId=RcqCRzmGP4Q80EkVSt531g QDMA_TRQ_MSIX_VF (0x4000) - QDMA_TRQ_MSIX_VF (0x4000) - 1.0 English - PG344 VF functions can access the MSIX table with offset (0x0000) from that function. The description for this register space is the same as QDMA_TRQ_MSIX (0x30000). qdma trq msix vf english https://docs.amd.com/r/1.0-English/pg344-pcie-dma-versal/Completion-Context-Structure?contentId=s7lH0Nw9hCCPBNW~CHkZkw Completion Context Structure - Completion Context Structure - 1.0 English - PG344 The completion context is used by the Completion Engine. Table 1. Completion Context Structure Definition Bit Bit Width Field Name Description [256:183] 17... context structure completion english https://docs.amd.com/r/1.0-English/pg344-pcie-dma-versal/Config-Block-BusDev-0x04 Config Block BusDev (0x04) - Config Block BusDev (0x04) - 1.0 English - PG344 Table 1. Config Block BusDev (0x04) Bit Index Default Access Type Description [15:0] PCIe IP RO bus_dev Bus, device, and function config block english https://docs.amd.com/r/1.0-English/pg344-pcie-dma-versal/PCIe-RQ/RC?contentId=3Fo0EXl1wE~aTs_bx5BRvQ PCIe RQ/RC - PCIe RQ/RC - 1.0 English - PG344 The PCIe Requester Request (RQ)/Requester Completion (RC) interface generates PCIeTLPs on the RQ bus and processes PCIe Completion TLPs from the RC bus. This... pcie rq rc english https://docs.amd.com/r/en-US/pg344-pcie-dma-versal/Descriptor-Context Descriptor Context - Descriptor Context - 2.0 English - PG344 The Descriptor Engine stores per queue configuration, status and control information in descriptor context that can be stored in block RAM or UltraRAM, and the... descriptor context english https://docs.amd.com/r/1.0-English/pg344-pcie-dma-versal/AXI4-Memory-Mapped-H2C-Flow?contentId=ZGJ5IbnRZ85lsFmBtvESyQ AXI4 Memory Mapped H2C Flow - AXI4 Memory Mapped H2C Flow - 1.0 English - PG344 Figure 1. AXI4 Memory Mapped Host to Card (H2C) Flow Diagram memory mapped flow english