https://docs.amd.com/r/en-US/pg210-25g-ethernet/STAT_HARD_RSFEC_RX_DELAY_REG-04A4?contentId=vVJX9bcKl9Ph~mt22HufNw
STAT_HARD_RSFEC_RX_DELAY_REG: 04A4 - STAT_HARD_RSFEC_RX_DELAY_REG: 04A4 - 5.1 English - PG210
Table 1. STAT_HARD_RSFEC_RX_DELAY_REG: 04A4 Bits Default Type Signal 10 0 RO stat_hard_rsfec_rx_delay This register indicates the HARD_RFSEC_RX_DELAY value, it...
stathardrxdelay
https://docs.amd.com/r/3.3-English/pg210-25g-ethernet/STAT_RX_RSFEC_STATUS_REG-043C
STAT_RX_RSFEC_STATUS_REG: 043C - STAT_RX_RSFEC_STATUS_REG: 043C - 3.3 English - PG210
Table 1. STAT_RX_RSFEC_STATUS_REG: 043C Bits Default Type Signal 0 1 RO LL stat_rx_rsfec_lane_alignment_status 1 1 RO LL stat_rx_rsfec_hi_ser
statrxregenglish
https://docs.amd.com/r/en-US/pg314-versal-mrmac/RSFEC-Compensation-ROM?contentId=BsyBfCskCpUXut6KDA~9rg
RSFEC Compensation ROM - RSFEC Compensation ROM - 3.1 English - PG314
Additional timestamp compensation can be obtained when RSFEC is active by enabling the RSFEC Compensation ROM. The user logic might want to enable this feature...
compensationromenglish
https://docs.amd.com/r/en-US/pg210-25g-ethernet/STAT_RX_RSFEC_STATUS_REG-043C?contentId=BGdMIuN6H_5pvgaPJaxtSA
STAT_RX_RSFEC_STATUS_REG: 043C - STAT_RX_RSFEC_STATUS_REG: 043C - 5.1 English - PG210
Table 1. STAT_RX_RSFEC_STATUS_REG: 043C Bits Default Type Signal 0 1 RO LL stat_rx_rsfec_lane_alignment_status 1 0 RO LH stat_rx_rsfec_hi_ser
statrxregenglish