https://docs.amd.com/r/2023.2-English/ug949-vivado-design-methodology/PCIE4C-to-HBM-AXI-Paths-within-SLR0?contentId=d0ai7s2ZssYAD2lBWtlihw
PCIE4C to HBM AXI Paths within SLR0 - PCIE4C to HBM AXI Paths within SLR0 - 2023.2 English - UG949
To achieve optimal timing QoR and minimize routing congestion when designing with HBM and PCIE4C, AMD recommends using the PCIE4C sites that are farthest away...
hbmaxipaths
https://docs.amd.com/r/2020.2-English/ug949-vivado-design-methodology/Resource-Planning-within-SLR0?contentId=LdvWMLOeMZFTQEMD6ywIUw
Resource Planning within SLR0 - Resource Planning within SLR0 - 2020.2 English - UG949
Proper management of the HBM AXI Interfaces and other logic within the SLR0 can provide optimal quality of results (QoR) and minimize routing congestion....
resource planningwithinenglish