https://docs.amd.com/r/en-US/pg156-ultrascale-pcie-gen3/s_axis_tx_tstrb?contentId=fEY7sMQgUw1Dcxj8x9a33Q
s_axis_tx_tstrb - s_axis_tx_tstrb - 4.4 English - PG156
The following table shows the Requester Request interface signals used to generate the s_axis_tx_tstrb signal bus. Table 1. Requester Request Interface Signals...
axistxenglish
https://docs.amd.com/r/en-US/pg156-ultrascale-pcie-gen3/m_axis_rx_tstrb-64-Bit-Interface-Only
m_axis_rx_tstrb (64-Bit Interface Only) - m_axis_rx_tstrb (64-Bit Interface Only) - 4.4 English -...
The following table shows the Requester Completion interface signals used to generate the m_axis_rx_tstrb signal bus. Table 1. RC Interface Signals for...
axisrxbitinterfaceenglish