https://docs.amd.com/r/en-US/pg230-vid-phy-controller/MISC-TXUSRCLK-Control-MISC_TXUSRCLK_CTRL-Register-0x0138
MISC TXUSRCLK Control (MISC_TXUSRCLK_CTRL) Register (0x0138) - MISC TXUSRCLK Control...
Table 1. MISC TXUSRCLK Control (MISC_TXUSRCLK_CTRL) Register Bit Default Value Access Type Description 0 0 RW CLKOUT1 OBUFTDS Output Enable. 0: disabled; 1:...
misccontrolctrlregister