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https://docs.amd.com/r/2021.2-English/ug899-vivado-io-clock-planning/Hard-Block-Planning-for-Versal-ACAP?contentId=5_xb~igPhwxRbxQsjC_joA Hard Block Planning for Versal ACAP - Hard Block Planning for Versal ACAP - 2021.2 English - UG899 GT components are updated from Common/Channel to a GT_QUAD granularity for Versal ACAP. To enable some of the GT sharing use cases, GT wizard flows are... hard block planning versal acap https://docs.amd.com/r/2023.2-English/ug899-vivado-io-clock-planning/CSV-File CSV File - CSV File - 2023.2 English - UG899 A CSV file is a standard file format used by FPGA and board designers to exchange information about device pins and pinout. For more information, see Importing... csv file english https://docs.amd.com/r/2023.2-English/ug899-vivado-io-clock-planning/Supported-Third-Party-PCB-Tools?contentId=4pNluFeGhxgineh8LOA2Ag Supported Third-Party PCB Tools - Supported Third-Party PCB Tools - 2023.2 English - UG899 To optimize the I/O assignments within the context of the entire board, AMD also supports Cadence Allegro FPGA System Planner and Mentor Graphics I/O Designer.... third party pcb tools supported english https://docs.amd.com/r/2024.2-English/ug899-vivado-io-clock-planning/Finding-Additional-Documentation?contentId=Q9GHhz2i9FRqSa3ju2DTag Finding Additional Documentation - Finding Additional Documentation - 2024.2 English - UG899 Technical Information Portal The AMD Technical Information Portal is an online tool that provides robust search and navigation for documentation using your web... additional documentation finding english https://docs.amd.com/r/en-US/ug899-vivado-io-clock-planning/Running-Memory-DRCs?contentId=fPWbG00eLIzA~qT4JZx8KQ Running Memory DRCs - Running Memory DRCs - 2025.2 English - UG899 After assigning or modifying pin assignments, you must run the default DRC rule deck on the elaborated or synthesized design using the Report DRC command as... running memory drcs english https://docs.amd.com/r/en-US/ug899-vivado-io-clock-planning/Creating-I/O-Port-Interfaces?contentId=2022jOY6P9yXFl3kp_tS2g Creating I/O Port Interfaces - Creating I/O Port Interfaces - 2025.2 English - UG899 To group multiple ports or buses together, you can create an interface. This aids in pin assignment by treating all of the interface ports as one group.... creating port interfaces english https://docs.amd.com/r/2024.2-English/ug899-vivado-io-clock-planning/Defining-Alternate-Compatible-Parts?contentId=ThrexIXSq8ieUJ37Cs3sYQ Defining Alternate Compatible Parts - Defining Alternate Compatible Parts - 2024.2 English - UG899 You can select compatible devices for the design to allow you to retarget the design to alternate AMD devices if necessary. The Vivado tools select compatible... compatible parts defining alternate english https://docs.amd.com/r/en-US/ug899-vivado-io-clock-planning/Viewing-DRC-Violation-Properties Viewing DRC Violation Properties - Viewing DRC Violation Properties - 2025.2 English - UG899 In the DRC window, right-click a violation message, and select Violations Properties. In the Violation Properties window, click the following views: General... viewing drc violation properties english https://docs.amd.com/r/2020.2-English/ug899-vivado-io-clock-planning/Removing-I/O-Ports-from-an-Interface Removing I/O Ports from an Interface - Removing I/O Ports from an Interface - 2020.2 English - UG899 To remove I/O ports, in the I/O Ports window right-click a port, and select Unassign from Interface. removing ports https://docs.amd.com/r/2020.2-English/ug899-vivado-io-clock-planning/Modifying-Memory-I/O-Ports Modifying Memory I/O Ports - Modifying Memory I/O Ports - 2020.2 English - UG899 You can manually modify memory I/O ports, such as swap pins, using the I/O Ports window or the Package Pins window. Both windows are expandable data tables,... modifying memory ports english https://docs.amd.com/r/2022.1-English/ug899-vivado-io-clock-planning/Importing-I/O-Ports Importing I/O Ports - Importing I/O Ports - 2022.1 English - UG899 Depending on the project type, you can use the following methods to import I/O ports: I/O Planning Project You can import XDC and CSV files into an empty I/O... importing ports english https://docs.amd.com/r/2024.2-English/ug899-vivado-io-clock-planning/Properties?contentId=5uH5lNjdyZddAPGIN3Yf7w Properties - Properties - 2024.2 English - UG899 The Properties window shows properties for a selected object. The title bar changes to reflect the type of object selected. In most cases, the Properties... properties english https://docs.amd.com/r/2022.2-English/ug899-vivado-io-clock-planning/Hard-Block-Planning-for-Versal-ACAP Hard Block Planning for Versal ACAP - Hard Block Planning for Versal ACAP - 2022.2 English - UG899 GT components are updated from Common/Channel to a GT_QUAD granularity for Versal ACAP. To enable some of the GT sharing use cases, GT wizard flows are... hard block planning versal acap https://docs.amd.com/r/2021.2-English/ug899-vivado-io-clock-planning/Netlist-I/O-Planning?contentId=XGz_8WRR_7b2jIG8O87hqg Netlist I/O Planning - Netlist I/O Planning - 2021.2 English - UG899 You can also perform I/O planning with a synthesized netlist. With this method, you use either a synthesized RTL project or a netlist project created with a... netlist planning english https://docs.amd.com/r/2020.2-English/ug899-vivado-io-clock-planning/Importing-an-XDC-File Importing an XDC File - Importing an XDC File - 2020.2 English - UG899 importing xdc file english https://docs.amd.com/r/2022.1-English/ug899-vivado-io-clock-planning/Querying-DRCs Querying DRCs - Querying DRCs - 2022.1 English - UG899 To get a list of the currently defined DRCs, use the get_drc_checks Tcl command. For more information, see section get_drc_checks in the Vivado Design Suite... querying drcs english https://docs.amd.com/r/2024.2-English/ug899-vivado-io-clock-planning/Generating-IBIS-Models?contentId=BQNT5Johi0AORje3phrljA Generating IBIS Models - Generating IBIS Models - 2024.2 English - UG899 The Input/Output Buffer Information Specification (IBIS) is a device modeling standard. IBIS allows for the development of behavioral models used to describe... generating ibis models english https://docs.amd.com/r/2021.2-English/ug899-vivado-io-clock-planning/Setting-Device-Configuration-Modes?contentId=SRuK1lW3REzbjwFWESdfRA Setting Device Configuration Modes - Setting Device Configuration Modes - 2021.2 English - UG899 Because Xilinx device configuration data is stored in CMOS latches, the device must be reconfigured each time it is powered up. The bitstream is loaded into... device configuration setting modes english https://docs.amd.com/r/2021.2-English/ug899-vivado-io-clock-planning/Determining-SSN-Analysis-Support?contentId=fcn2A51mhLS9vu8NgisMWA Determining SSN Analysis Support - Determining SSN Analysis Support - 2021.2 English - UG899 Not all devices support SSN analysis. To determine whether SSN analysis is available for the device targeted by the design open in memory, enter the following... analysis support determining ssn english https://docs.amd.com/r/2024.2-English/ug899-vivado-io-clock-planning/Viewing-DRC-Violation-Properties?contentId=2v7fvh_xGs6lGjPxqR_~JA Viewing DRC Violation Properties - Viewing DRC Violation Properties - 2024.2 English - UG899 In the DRC window, right-click a violation message, and select Violations Properties. In the Violation Properties window, click the following views: General... viewing drc violation properties english https://docs.amd.com/r/2024.2-English/ug899-vivado-io-clock-planning/Creating-Custom-DRCs?contentId=cXANhL09mxNwg1w9KA4Qwg Creating Custom DRCs - Creating Custom DRCs - 2024.2 English - UG899 You can also use Tcl commands, such as create_drc_check and create_drc_violation, to create custom DRCs for use in the Vivado Design Suite. For more... creating custom drcs english https://docs.amd.com/r/2024.2-English/ug899-vivado-io-clock-planning/Revision-History?contentId=zElVFrlFrDsU2zkdke9LNA Revision History - Revision History - 2024.2 English - UG899 The following table shows the revision history for this document. Section Revision Summary 11/13/2024 Version 2024.2 Navigating Content by Design Process, I/O... revision history english https://docs.amd.com/r/2023.2-English/ug899-vivado-io-clock-planning/I/O-and-Clock-Planning-Features?contentId=U712TjoUHH1cWccMgjNR3A I/O and Clock Planning Features - I/O and Clock Planning Features - 2023.2 English - UG899 The following table shows the features supported for each type of project. Table 1. I/O and Clock Planning Features Feature I/O Planning Project RTL Design... planning features clock english https://docs.amd.com/r/2021.2-English/ug899-vivado-io-clock-planning/Removing-I/O-Placement-Constraints?contentId=_Xd6gAz8ipRuf~YLNNLn2g Removing I/O Placement Constraints - Removing I/O Placement Constraints - 2021.2 English - UG899 To remove placement constraints, select the placed logic, right-click, and select Unplace. removing placement constraints english https://docs.amd.com/r/2022.1-English/ug899-vivado-io-clock-planning/Hard-Block-Planning-for-Versal-ACAP?contentId=0sHCm5~KzaXHqR31ssn_1A Hard Block Planning for Versal ACAP - Hard Block Planning for Versal ACAP - 2022.1 English - UG899 GT components are updated from Common/Channel to a GT_QUAD granularity for Versal ACAP. To enable some of the GT sharing use cases, GT wizard flows are... hard block planning versal acap https://docs.amd.com/r/2024.2-English/ug899-vivado-io-clock-planning/Running-Memory-DRCs?contentId=G3rqZxxpmiDGPkGyT5EW1g Running Memory DRCs - Running Memory DRCs - 2024.2 English - UG899 After assigning or modifying pin assignments, you must run the default DRC rule deck on the elaborated or synthesized design using the Report DRC command as... running memory drcs english https://docs.amd.com/r/2024.2-English/ug899-vivado-io-clock-planning/Placing-I/O-Ports-into-I/O-Banks?contentId=vYNwPLEzXNUit4Gx06E9xA Placing I/O Ports into I/O Banks - Placing I/O Ports into I/O Banks - 2024.2 English - UG899 To place I/O ports into I/O banks: In the I/O Ports window, select an individual I/O port, a group of I/O ports, or interfaces. Use one of the following... placing ports banks english https://docs.amd.com/r/2021.1-English/ug899-vivado-io-clock-planning/Multifunction-Pins?contentId=rf5PNxWeIxDkp2w7vG8Uaw Multifunction Pins - Multifunction Pins - 2021.1 English - UG899 The Package Pins window contains several data types that display in columns similar to a spreadsheet. In this window, you can: Flatten, filter, and sort data.... multifunction pins english https://docs.amd.com/r/2022.1-English/ug899-vivado-io-clock-planning/I/O-Bank-Resources?contentId=AC6X9eijdQpc9Tjlbf8RAw I/O Bank Resources - I/O Bank Resources - 2022.1 English - UG899 You can select I/O resources in any of the I/O planning windows and their corresponding data is highlighted in all other windows as shown in the Clock Regions... bank resources english https://docs.amd.com/r/2021.2-English/ug899-vivado-io-clock-planning/Modifying-Memory-I/O-Ports Modifying Memory I/O Ports - Modifying Memory I/O Ports - 2021.2 English - UG899 You can manually modify memory I/O ports, such as swap pins, using the I/O Ports window or the Package Pins window. Both windows are expandable data tables,... modifying memory ports english https://docs.amd.com/r/2023.2-English/ug899-vivado-io-clock-planning/Placing-I/O-Ports-into-I/O-Banks Placing I/O Ports into I/O Banks - Placing I/O Ports into I/O Banks - 2023.2 English - UG899 To place I/O ports into I/O banks: In the I/O Ports window, select an individual I/O port, a group of I/O ports, or interfaces. Use one of the following... placing ports banks english https://docs.amd.com/r/2021.2-English/ug899-vivado-io-clock-planning/Manually-Assigning-Signal-Groups?contentId=bkCAoGeJdwvZ_qv8M~Nv_w Manually Assigning Signal Groups - Manually Assigning Signal Groups - 2021.2 English - UG899 To manually assign signal groups to byte lanes: In the Mem Byte Group column in the following figure, click the drop-down list next to a bank. Select a signal... signal groups manually assigning english https://docs.amd.com/r/2021.2-English/ug899-vivado-io-clock-planning/Exporting-IBIS-Models Exporting IBIS Models - Exporting IBIS Models - 2021.2 English - UG899 To better understand the signal integrity at the system level, PCB designers often need to simulate the design with IBIS models. Designers must consider signal... exporting ibis models english https://docs.amd.com/r/2024.2-English/ug899-vivado-io-clock-planning/Manually-Assigning-Signal-Groups?contentId=5nQFN~Y3WhxeJxF8ohPItw Manually Assigning Signal Groups - Manually Assigning Signal Groups - 2024.2 English - UG899 To manually assign signal groups to byte lanes: In the Mem Byte Group column in the following figure, click the drop-down list next to a bank. Select a signal... signal groups manually assigning english https://docs.amd.com/r/2021.1-English/ug899-vivado-io-clock-planning/SSN-Analysis SSN Analysis - SSN Analysis - 2021.1 English - UG899 To generate an estimate of potential noise disruptions, run SSN analysis as described in Working with SSN Analysis. Xilinx recommends that you address... ssn analysis english https://docs.amd.com/r/2023.2-English/ug899-vivado-io-clock-planning/Please-Read-Important-Legal-Notices?contentId=Q8IAJRwzfLPSsGHo5Q_eyA Please Read: Important Legal Notices - Please Read: Important Legal Notices - 2023.2 English - UG899 The information presented in this document is for informational purposes only and may contain technical inaccuracies, omissions, and typographical errors. The... important legal notices please read english https://docs.amd.com/r/2024.2-English/ug899-vivado-io-clock-planning/Using-the-Memory-Bank/Byte-Planner?contentId=LllgLQLWW6cwuyvqI8sZIg Using the Memory Bank/Byte Planner - Using the Memory Bank/Byte Planner - 2024.2 English - UG899 The I/O Planning view layout includes the I/O Ports and Package Pins windows. If UltraScale architecture Memory IP exists in the design, the banners of both... the memory using bank byte planner https://docs.amd.com/r/2023.2-English/ug899-vivado-io-clock-planning/Creating-Custom-DRCs?contentId=_J9m2Dbrz4V2VhsrtIKOMw Creating Custom DRCs - Creating Custom DRCs - 2023.2 English - UG899 You can also use Tcl commands, such as create_drc_check and create_drc_violation, to create custom DRCs for use in the Vivado Design Suite. For more... creating custom drcs english https://docs.amd.com/r/2024.2-English/ug899-vivado-io-clock-planning/Report-Methodology?contentId=V_2S0ZLbBPTZzwOK_Y6FsQ Report Methodology - Report Methodology - 2024.2 English - UG899 In 2016.1, some checks were moved from report_drc into the new report_methodology command. These checks include constraints and other rules that verify the... report methodology english https://docs.amd.com/r/2021.2-English/ug899-vivado-io-clock-planning/Prohibiting-I/O-Pins-and-I/O-Banks?contentId=QR8M1aHvdb7GD33EnsWKig Prohibiting I/O Pins and I/O Banks - Prohibiting I/O Pins and I/O Banks - 2021.2 English - UG899 The I/O Planning view layout provides an interface to selectively prohibit port placement onto individual I/O pins, groups of I/O pins, or I/O banks. You can... pins banks english https://docs.amd.com/r/2023.2-English/ug899-vivado-io-clock-planning/Part-Compatibility?contentId=7qjhXy1tKkteYdoLRhMS8A Part Compatibility - Part Compatibility - 2023.2 English - UG899 Set the part compatibility for your design as described in Defining Alternate Compatible Parts. The Vivado IDE identifies the pins that are common to all... part compatibility english https://docs.amd.com/r/2022.2-English/ug899-vivado-io-clock-planning/Viewing-SSN-Results Viewing SSN Results - Viewing SSN Results - 2022.2 English - UG899 After the analysis is complete, the Noise window opens. Figure 1. Noise Window Click the links on the left side of the window to view different information... viewing ssn results english https://docs.amd.com/r/2024.2-English/ug899-vivado-io-clock-planning/Swapping-Previously-Placed-I/O-Ports?contentId=w2vCfC3nwaNo9F9b7Et1Uw Swapping Previously Placed I/O Ports - Swapping Previously Placed I/O Ports - 2024.2 English - UG899 To swap the location of two placed I/O ports that are already assigned: Select two I/O ports from any of the available windows. Right-click, and select Swap... swapping previously placed ports english https://docs.amd.com/r/2020.2-English/ug899-vivado-io-clock-planning/Training-Resources Training Resources - Training Resources - 2020.2 English - UG899 Xilinx provides a variety of training courses and QuickTake videos to help you learn more about the concepts presented in this document. Use these links to... training resources english https://docs.amd.com/r/2024.2-English/ug899-vivado-io-clock-planning/SSN-Analysis?contentId=7illAzaBTTVE6uKQuNHhPA SSN Analysis - SSN Analysis - 2024.2 English - UG899 To generate an estimate of potential noise disruptions, run SSN analysis as described in Working with SSN Analysis. AMD recommends that you address... ssn analysis english https://docs.amd.com/r/2021.1-English/ug899-vivado-io-clock-planning/Removing-I/O-Ports-from-an-Interface Removing I/O Ports from an Interface - Removing I/O Ports from an Interface - 2021.1 English - UG899 To remove I/O ports, in the I/O Ports window right-click a port, and select Unassign from Interface. removing ports https://docs.amd.com/r/2022.1-English/ug899-vivado-io-clock-planning/Tcl-Command-Example-for-Running-DRCs Tcl Command Example for Running DRCs - Tcl Command Example for Running DRCs - 2022.1 English - UG899 report_drc -ruledecks default -file C:/Data/DRC_Rpt1.txt for running tcl command example drcs https://docs.amd.com/r/2022.1-English/ug899-vivado-io-clock-planning/RTL-I/O-Planning?contentId=ouPONvpOP_lKzYhcGMCpnw RTL I/O Planning - RTL I/O Planning - 2022.1 English - UG899 You can perform I/O planning in an elaborated RTL project. With this method, you use an RTL design, which optionally includes IP cores from the Vivado IP... rtl planning english https://docs.amd.com/r/2024.2-English/ug899-vivado-io-clock-planning/Importing-a-CSV-File?contentId=loUIZhn8xyMNfH0Hljki3w Importing a CSV File - Importing a CSV File - 2024.2 English - UG899 You can import a CSV file to populate the I/O Ports window within the I/O Planning layout view. You can then assign these I/O ports to physical package pins to... csv file importing english https://docs.amd.com/r/2024.2-English/ug899-vivado-io-clock-planning/Interfacing-with-the-PCB-Design?contentId=7Z2hX6eMrZ6KHQSES3evVA Interfacing with the PCB Design - Interfacing with the PCB Design - 2024.2 English - UG899 The Vivado pin planner provides an effective way to select the pin assignments for the design. Choosing correct resources enables a faster and cleaner design... pcb design interfacing english https://docs.amd.com/r/2020.2-English/ug899-vivado-io-clock-planning/Using-the-Advanced-IO-Planner Using the Advanced IO Planner - Using the Advanced IO Planner - 2020.2 English - UG899 To create a new IO planning project, complete the following steps: Launch Vivado and create a new project targeting a Versal device as described in this step.... using advanced io planner english https://docs.amd.com/r/2020.2-English/ug899-vivado-io-clock-planning/Running-Memory-DRCs?contentId=45NmQPaCUYJjBe02xtghTw Running Memory DRCs - Running Memory DRCs - 2020.2 English - UG899 After assigning or modifying pin assignments, you must run the default DRC rule deck on the elaborated or synthesized design using the Report DRC command as... running memory drcs english https://docs.amd.com/r/2024.2-English/ug899-vivado-io-clock-planning/Querying-DRCs?contentId=kaxtdAwNvPUUiqy6FnKaIQ Querying DRCs - Querying DRCs - 2024.2 English - UG899 To get a list of the currently defined DRCs, use the get_drc_checks Tcl command. For more information, see section get_drc_checks in the Vivado Design Suite... querying drcs english https://docs.amd.com/r/2022.1-English/ug899-vivado-io-clock-planning/Setting-Device-Configuration-Modes Setting Device Configuration Modes - Setting Device Configuration Modes - 2022.1 English - UG899 Because Xilinx device configuration data is stored in CMOS latches, the device must be reconfigured each time it is powered up. The bitstream is loaded into... device configuration setting modes english https://docs.amd.com/r/en-US/ug899-vivado-io-clock-planning/Sorting-DRC-Violations?contentId=EClwP~F538xqAX6B4JdtUQ Sorting DRC Violations - Sorting DRC Violations - 2025.2 English - UG899 To sort DRC violations by severity, click the Severity column header as follows: Click the column header to sort in an increasing order. Click the column... sorting drc violations english https://docs.amd.com/r/2022.2-English/ug899-vivado-io-clock-planning/Viewing-SSN-Results?contentId=vRw6ikIYkumWVtjy9qlA1w Viewing SSN Results - Viewing SSN Results - 2022.2 English - UG899 After the analysis is complete, the Noise window opens. Figure 1. Noise Window Click the links on the left side of the window to view different information... viewing ssn results english https://docs.amd.com/r/2022.1-English/ug899-vivado-io-clock-planning/RTL-I/O-Planning RTL I/O Planning - RTL I/O Planning - 2022.1 English - UG899 You can perform I/O planning in an elaborated RTL project. With this method, you use an RTL design, which optionally includes IP cores from the Vivado IP... rtl planning english https://docs.amd.com/r/2022.2-English/ug899-vivado-io-clock-planning/Setting-I/O-Port-Direction Setting I/O Port Direction - Setting I/O Port Direction - 2022.2 English - UG899 To set I/O port direction, use any of the following methods: For I/O planning projects only: In the Direction column of the I/O Ports window, click a port and... setting port direction english