https://docs.amd.com/r/en-US/pg432-versal-ai-edge-series-gen-2-isp/RGB888/YUV444-8-bit-Interleaved-Without-YUV-Align?contentId=1OSO8AOqOXzrVTCQd4gGTw
RGB888/YUV444 8-bit Interleaved Without YUV Align - RGB888/YUV444 8-bit Interleaved Without YUV...
Figure 1. RGB888/YUV444 8-bit Interleaved Without YUV Align
bitinterleavedwithoutyuvalign
https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/2237988887/Zynq+UltraScale+MPSoC+VCU+TRD+2021.2+-+PL+DDR+HDMI+YUV444+Video+Capture+and+Display
Zynq UltraScale+ MPSoC VCU TRD 2021.2 - YUV444 Video Capture and Display - AMD Adaptive Computing...
https://docs.amd.com/r/en-US/pg432-versal-ai-edge-series-gen-2-isp/RGB888/YUV444-10-bit-Interleaved-with-YUV-Align?contentId=_tKGRzl2CopfJqIi3SKaqw
RGB888/YUV444 10-bit Interleaved with YUV Align - RGB888/YUV444 10-bit Interleaved with YUV Align -...
Figure 1. RGB888/YUV444 10-bit Interleaved with YUV Align The padded data is taken from the following register: Table 1. MI_ARGB_PADDING Register Register Name...
bitinterleavedyuvalign