https://ez.analog.com/rf/wide-band-rf-transceivers/design-support-adrv9008-1-adrv9008-2-adrv9009/f/q-a/571268/adrv9009-zu11eg-jesd204b-error--22-vcxo-frequency-change/498147
ADRV9009-ZU11EG JESD204B Error -22 (VCXO Frequency Change) - Q&A - Support ADRV9008x/ADRV9009 -...
Question: Where is the system configuration going wrong to not setup the TX JESD204 link correctly for the new clock rates? Setup: We are currently working with
https://ez.analog.com/linux-software-drivers/f/q-a/168101/ltc2983-device-tree-zynqmp-ultarscale-adrv9009-zu11eg/398334
LTC2983 & Device Tree (ZynqMP Ultarscale+ ADRV9009-ZU11EG) - Q&A - Linux Software Drivers -...
Hello, I'm looking to customize the device tree on my linux target to incorporate the LTC2983 temp sensor. I've been referencing SPI device initialization here
device tree
https://ez.analog.com/fpga/f/q-a/582918/zu11eg-rfsom-building-correct-vivado-project-for-use-with-petalinux/528652
ZU11EG RFSOM Building Correct Vivado Project for use with Petalinux - Q&A - FPGA Reference Designs...
We are trying to use the github code here (main branch) to build an XSA file. We made sure to generate all of the libs and IPs with 2022.2 since that is what is
https://ez.analog.com/linux-software-drivers/f/q-a/168101/ltc2983-device-tree-zynqmp-ultarscale-adrv9009-zu11eg/382451
LTC2983 & Device Tree (ZynqMP Ultarscale+ ADRV9009-ZU11EG) - Q&A - Linux Software Drivers -...
Hello, I'm looking to customize the device tree on my linux target to incorporate the LTC2983 temp sensor. I've been referencing SPI device initialization here
device tree
https://ez.analog.com/fpga/f/q-a/539645/using-pps-adrv9009-zu11eg-on-adrv2crr-fmc?ReplyFilter=Answers&ReplySortBy=Answers&ReplySortOrder=Descending
Using PPS ADRV9009-ZU11EG on ADRV2CRR-FMC - Q&A - FPGA Reference Designs - EngineerZone
Hi, We plan to use GPS PPS on ADRV9009-ZU11EG. Do I need to use a reference clock generator that comes with a PPS output? Any particular board do you suggest