https://ez.analog.com/fpga/f/q-a/586635/zc706-ad9081-building-hdl/539915
ZC706+AD9081 building HDL - Q&A - FPGA Reference Designs - EngineerZone
Hi : I do command make to build HDL following ADI's instruction (analogdevicesinc.github.io/.../build_hdl.html But it's failed . following picture 1 . and file
fpga reference designsbuildinghdlq
https://ez.analog.com/rf/mixed-signal-front-ends-mxfe/f/q-a/561422/ad9081-ad9082-evaluation-board-schematics
AD9081/AD9082 Evaluation Board Schematics - Q&A - Mixed-Signal Front Ends (MxFE) - EngineerZone
https://ez.analog.com/fpga/f/q-a/586635/zc706-ad9081-building-hdl/539734
ZC706+AD9081 building HDL - Q&A - FPGA Reference Designs - EngineerZone
Hi : I do command make to build HDL following ADI's instruction (analogdevicesinc.github.io/.../build_hdl.html But it's failed . following picture 1 . and file
fpga reference designsbuildinghdlq