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https://ez.analog.com/fpga/?src=FeaturedPlaces FPGA Reference Designs - EngineerZone EngineerZone technical forum that provides customer support for Analog Devices FPGA Reference Designs. fpga reference designs https://ez.analog.com/fpga/f/q-a/102247/square-wave-output-using-fmcdaq2/306121 Square wave output using fmcdaq2 - Q&A - FPGA Reference Designs - EngineerZone Dear EngineerZone community Please support. I am currently creating a communication system. The concept is to generate an information signal with vc707 and... fpga reference designssquare waveoutputusing https://ez.analog.com/fpga/f/q-a/582601/building-an-hdl-project/527965 Building an HDL Project - Q&A - FPGA Reference Designs - EngineerZone Hi, I am trying to Build an HDL project of one of the reference designs but am failing when invoking make. I am currently following this: Build an HDL project fpga reference designsproject qbuildinghdl https://ez.analog.com/fpga/f/q-a/563185/zcu102-adrv9009-hdl-implementation-fail/487891 ZCU102 + ADRV9009 HDL implementation fail - Q&A - FPGA Reference Designs - EngineerZone I have downloaded the latest HDL for ZCU102 attached with ADRV9008-1W. HDL version is for ADRV9009. I have only modified the design to have hierarchy blocks in... fpga reference designshdlimplementationfail https://ez.analog.com/fpga/f/q-a/582601/building-an-hdl-project/527791 Building an HDL Project - Q&A - FPGA Reference Designs - EngineerZone Hi, I am trying to Build an HDL project of one of the reference designs but am failing when invoking make. I am currently following this: Build an HDL project fpga reference designsproject qbuildinghdl https://ez.analog.com/fpga/f/q-a/582601/building-an-hdl-project/530204 Building an HDL Project - Q&A - FPGA Reference Designs - EngineerZone Hi, I am trying to Build an HDL project of one of the reference designs but am failing when invoking make. I am currently following this: Build an HDL project fpga reference designsproject qbuildinghdl https://ez.analog.com/fpga/f/q-a/102247/square-wave-output-using-fmcdaq2 Square wave output using fmcdaq2 - Q&A - FPGA Reference Designs - EngineerZone Dear EngineerZone community Please support. I am currently creating a communication system. The concept is to generate an information signal with vc707 and... fpga reference designssquare waveoutputusing https://ez.analog.com/fpga/f/q-a Q&A - FPGA Reference Designs - EngineerZone fpga reference designsq https://ez.analog.com/fpga/f/q-a/586635/zc706-ad9081-building-hdl/539915 ZC706+AD9081 building HDL - Q&A - FPGA Reference Designs - EngineerZone Hi : I do command make to build HDL following ADI's instruction (analogdevicesinc.github.io/.../build_hdl.html But it's failed . following picture 1 . and file fpga reference designsbuildinghdlq https://ez.analog.com/fpga/f/q-a/586635/zc706-ad9081-building-hdl/539734 ZC706+AD9081 building HDL - Q&A - FPGA Reference Designs - EngineerZone Hi : I do command make to build HDL following ADI's instruction (analogdevicesinc.github.io/.../build_hdl.html But it's failed . following picture 1 . and file fpga reference designsbuildinghdlq https://ez.analog.com/fpga/f/q-a/582601/building-an-hdl-project/529521 Building an HDL Project - Q&A - FPGA Reference Designs - EngineerZone Hi, I am trying to Build an HDL project of one of the reference designs but am failing when invoking make. I am currently following this: Build an HDL project fpga reference designsproject qbuildinghdl https://ez.analog.com/fpga/f/q-a/582163/ad9209-core-synchronisation/529108 AD9209 Core Synchronisation - Q&A - FPGA Reference Designs - EngineerZone I am using two AD9209, where all x8 Lanes of each data converters shall be used. Logic device is Xilinx FPGA GTY Transceivers Using a single core to achieve... fpga reference designscoresynchronisationq https://ez.analog.com/fpga/f/q-a/102247/square-wave-output-using-fmcdaq2/309852 Square wave output using fmcdaq2 - Q&A - FPGA Reference Designs - EngineerZone Dear EngineerZone community Please support. I am currently creating a communication system. The concept is to generate an information signal with vc707 and... fpga reference designssquare waveoutputusing https://ez.analog.com/fpga/f/q-a/582601/building-an-hdl-project/529748 Building an HDL Project - Q&A - FPGA Reference Designs - EngineerZone Hi, I am trying to Build an HDL project of one of the reference designs but am failing when invoking make. I am currently following this: Build an HDL project fpga reference designsproject qbuildinghdl https://ez.analog.com/fpga/f/q-a/102247/square-wave-output-using-fmcdaq2/305398 Square wave output using fmcdaq2 - Q&A - FPGA Reference Designs - EngineerZone Dear EngineerZone community Please support. I am currently creating a communication system. The concept is to generate an information signal with vc707 and... fpga reference designssquare waveoutputusing https://ez.analog.com/fpga/f/q-a/592329/adv7511-on-custom-board-not-working ADV7511 on custom board not working - Q&A - FPGA Reference Designs - EngineerZone Hi, I am working to use ADV7511 hdmi output on a custom Zynq 7100 board. Have you solved the problem regarding the output of the adv7511? I'm currently... fpga reference designscustom boardnot working https://ez.analog.com/fpga/f/q-a/582601/building-an-hdl-project/529974 Building an HDL Project - Q&A - FPGA Reference Designs - EngineerZone Hi, I am trying to Build an HDL project of one of the reference designs but am failing when invoking make. I am currently following this: Build an HDL project fpga reference designsproject qbuildinghdl https://ez.analog.com/fpga/f/q-a/568424/functionality-of-axi_adcfifo-and-axi_dacfifo-with-mig-controller/490336 Functionality of AXI_ADCFIFO and AXI_DACFIFO with MIG Controller - Q&A - FPGA Reference Designs -... Hello Filip_Gherman AdrianC and Team , I am using ADI product ADRV9008-1W with ZCU102 and 2021_r1 HDL design. According to our need the design is modified in...