https://www.electronicdesign.com/news/products/article/21776111/testbench-platform-and-language-take-on-analog-signoff
Testbench Platform And Language Take On Analog Signoff | Electronic Design
The addition of the VIPer test extension language, improved performance of the binary test database, and availability of electrical verification IP (EVP) for...
take onanalog signofftestbenchplatformlanguage
https://www.ansys.com/it-it/resource-center/webinar/signal-workflow-signoff
Analog and Mixed Signal Workflows for Power and Reliability Signoff for SerDes IP and PMIC
Learn how AMS workflows based on Ansys Totem enables you to design the next generation of SerDes IP or PMIC for cutting-edge applications.
mixed signal