https://www.vlsimentor.com/ucie/cache-coherency-in-chiplets
UCIe Cache Coherency in Chiplets · VLSI Mentor
How several chiplets cache one line and still guarantee no illegal read — the directory that tracks owner and sharers, why a response bitmap and not a counter...
cache coherencyuciechipletsvlsimentor
https://www.eudoxuspress.com/index.php/pub/article/view/5479/4133
View of Cache Coherency and NUMA Balancing Performance Pathologies in AMD SEV-SNP Confidential...
cache coherencyamd sevviewnumabalancing