https://www.fpgarelated.com/showarticle/9.php
A Bit Bucket had Holes - Christopher Felton
Christopher Felton reviews TierLogic's multi-layer FPGA shutdown, compares it to Tabula's virtual 3D idea, and explores effects on ultra-dense FPGA design
a bitchristopher feltonbucketholes
https://dsprelated.com/showarticle/194/python-scipy-signal-iir-filtering-an-example.php
Python scipy.signal IIR Filtering: An Example - Christopher Felton
Example using Python scipy.signal to design IIR filters for PWM demodulation, comparing filtfilt, staged IIR, high-order FIR, spectrums and MyHDL.
python scipyan examplechristopher feltonsignaliir
https://www.embeddedrelated.com/showarticle/158/how-to-estimate-encoder-velocity-without-making-stupid-mistakes-part-i.php
scipy.signal calling all developers - Christopher Felton
SciPy.signal needs contributors. Learn why the package matters for DSP, what it already supports, and how you can get involved.
all developerschristopher feltonscipysignalcalling