ug1344 - Robuta Search

https://docs.amd.com/r/2022.2-English/ug1344-versal-architecture-libraries/MMCME5 MMCME5 - MMCME5 - 2022.2 English - Primitive: Mixed Mode Clock Manager (MMCM) - UG1344 Primitive: Mixed Mode Clock Manager (MMCM) mixed mode english primitive https://docs.amd.com/r/2021.2-English/ug1344-versal-architecture-libraries/LUT6CY LUT6CY - LUT6CY - 2021.2 English - Primitive: 6-Bit Look-Up Table with Carry - UG1344 Primitive: 6-Bit Look-Up Table with Carry https://docs.amd.com/r/2021.2-English/ug1344-versal-architecture-libraries/NOC_NMU512?contentId=eHd147Jc3IDgHMA9mbzBLA NOC_NMU512 - NOC_NMU512 - 2021.2 English - Primitive: NoC Master Unit - UG1344 Primitive: NoC Master Unit master unit noc english primitive https://docs.amd.com/r/2022.1-English/ug1344-versal-architecture-libraries/XPIO_VREF?contentId=hoq2SBmLr11XbmqHembj2Q XPIO_VREF - XPIO_VREF - 2022.1 English - Primitive: VREF Scan - UG1344 Primitive: VREF Scan english primitive scan https://docs.amd.com/r/2021.2-English/ug1344-versal-architecture-libraries/LUT6?contentId=z6lS6cC9pFKY8zGP0EqZIA LUT6 - LUT6 - 2021.2 English - Primitive: 6-Bit Look-Up Table - UG1344 Primitive: 6-Bit Look-Up Table look up english primitive https://docs.amd.com/r/2021.2-English/ug1344-versal-architecture-libraries/NOC_NSU512?contentId=p3S_fHxgbt6n2iZUpuayjg NOC_NSU512 - NOC_NSU512 - 2021.2 English - Primitive: Noc Slave Unit - UG1344 Primitive: Noc Slave Unit slave unit noc english primitive https://docs.amd.com/r/2022.1-English/ug1344-versal-architecture-libraries/NOC_NCRB?contentId=IHDwBmUpWPh88dvAXv_nAw NOC_NCRB - NOC_NCRB - 2022.1 English - Primitive: NoC Clock Reconvergent Buffer - UG1344 Primitive: NoC Clock Reconvergent Buffer noc ncrb english primitive clock https://docs.amd.com/r/2023.2-English/ug1344-versal-architecture-libraries/RAM32X1S RAM32X1S - RAM32X1S - 2023.2 English - Primitive: 32-Deep by 1-Wide Static Synchronous RAM - UG1344 Primitive: 32-Deep by 1-Wide Static Synchronous RAM https://docs.amd.com/r/2021.2-English/ug1344-versal-architecture-libraries/IOBUF_DCIEN?contentId=6Ldg~k8hM1_iKVtdF7X02A IOBUF_DCIEN - IOBUF_DCIEN - 2021.2 English - Primitive: Input/Output Buffer DCI Enable - UG1344 Primitive: Input/Output Buffer DCI Enable https://docs.amd.com/r/2022.1-English/ug1344-versal-architecture-libraries/IOBUF?contentId=tpVRr~ozTfVvadqPEdFIyw IOBUF - IOBUF - 2022.1 English - Primitive: Input/Output Buffer - UG1344 Primitive: Input/Output Buffer input output english primitive buffer https://docs.amd.com/r/2023.2-English/ug1344-versal-architecture-libraries/Xilinx-Parameterized-Macros Xilinx Parameterized Macros - Xilinx Parameterized Macros - 2023.2 English - UG1344 About Xilinx Parameterized Macros This section describes Xilinx Parameterized Macros that can be used with Versal architecture Prime series. The macros are... xilinx macros english https://docs.amd.com/r/2022.2-English/ug1344-versal-architecture-libraries/BUFGCTRL BUFGCTRL - BUFGCTRL - 2022.2 English - Primitive: General Clock Control Buffer - UG1344 Primitive: General Clock Control Buffer english primitive general clock control https://docs.amd.com/r/2022.1-English/ug1344-versal-architecture-libraries/XPLL?contentId=x4qJ87Kf6JQXIo7jqTmSLA XPLL - XPLL - 2022.1 English - Primitive: XPIO PLL - UG1344 xpll english primitive https://docs.amd.com/r/2021.2-English/ug1344-versal-architecture-libraries/BUFGMUX_CTRL?contentId=fs8FhggP6I07Ylzh4jL9bA BUFGMUX_CTRL - BUFGMUX_CTRL - 2021.2 English - Primitive: 2-to-1 General Clock MUX Buffer - UG1344 Primitive: 2-to-1 General Clock MUX Buffer https://docs.amd.com/r/2021.1-English/ug1344-versal-architecture-libraries/IBUFDS_GTE5?contentId=oAHH3KFB9RcZAMgF8oH9Gw IBUFDS_GTE5 - IBUFDS_GTE5 - 2021.1 English - Primitive: Gigabit Transceiver Buffer - UG1344 Primitive: Gigabit Transceiver Buffer english primitive gigabit transceiver buffer