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https://docs.amd.com/r/2023.2-English/ug1393-vitis-application-acceleration/Debugging-OpenCL-Kernels?contentId=Q2E5b_iNs5W6D3yrLIozWA Debugging OpenCL Kernels - Debugging OpenCL Kernels - 2023.2 English - UG1393 For OpenCL kernels, additional runtime checks can be performed during software emulation. These additional checks include: Checking whether an OpenCL kernel... debugging opencl kernels english https://docs.amd.com/r/2022.1-English/ug1393-vitis-application-acceleration/Adding-C-Models-to-RTL-Kernels?contentId=a21jxT7BLIpYqZ345K~nSg Adding C-Models to RTL Kernels - Adding C-Models to RTL Kernels - 2022.1 English - UG1393 RTL kernels support the hardware emulation build, and the hardware build described in Build Targets, but an RTL kernel in its native form does not support... adding c models rtl kernels https://docs.amd.com/r/2020.2-English/ug1393-vitis-application-acceleration/query?contentId=KqsQg4qMVRPUnAjUGENImQ query - query - 2020.2 English - UG1393 Important: This option cannot be used with embedded processor platforms. The query command returns detailed card status information in human readable format.... query english https://docs.amd.com/r/2023.1-English/ug1393-vitis-application-acceleration/Profile-Summary Profile Summary - Profile Summary - 2023.1 English - UG1393 The xrt.run_summary file can be loaded into Vitis Analyzer and an example of the results is shown in the picture. The application run summary is presented... profile summary english https://docs.amd.com/r/2022.1-English/ug1393-vitis-application-acceleration/Writing-a-Custom-Makefile?contentId=Sk4ISTL88l0lrF6j1rSU2w Writing a Custom Makefile - Writing a Custom Makefile - 2022.1 English - UG1393 Your custom Makefile should provide similar functions as the template Makefile. The basic steps to compile in VSC are similar to other Vitis tool flows, as... a custom writing makefile english https://docs.amd.com/r/2022.2-English/ug1393-vitis-application-acceleration/HW-Interfaces?contentId=LCnbo6cI6Ch7x8y6XgFXJw HW Interfaces - HW Interfaces - 2022.2 English - UG1393 The kernel interfaces are used to exchange the data with the host application, other kernels, or device I/Os. Non-software controlled kernels have the... hw interfaces english https://docs.amd.com/r/2022.2-English/ug1393-vitis-application-acceleration/xstatus-Commands?contentId=1ASRBcBTNxvZlqA5_2cllA xstatus Commands - xstatus Commands - 2022.2 English - UG1393 commands english https://docs.amd.com/r/2023.2-English/ug1393-vitis-application-acceleration/MATLAB-API-for-AI-Engine-Graphs?contentId=rQrsq~rHdPAKur2ZqpyHUA MATLAB API for AI Engine Graphs - MATLAB API for AI Engine Graphs - 2023.2 English - UG1393 Here is the list of AI Engine specific APIs and their usage in integrating the traffic generators. With the MATLAB API you can create the traffic generator... api for ai matlab engine graphs english https://docs.amd.com/r/2023.2-English/ug1393-vitis-application-acceleration/Profile-Summary?contentId=t8czUG6fYQknYJAwdy79Kw Profile Summary - Profile Summary - 2023.2 English - UG1393 The xrt.run_summary file can be loaded into Vitis Analyzer and an example of the results is shown in the picture. The application run summary is presented... profile summary english https://docs.amd.com/r/2021.2-English/ug1393-vitis-application-acceleration/xclbin-Information?contentId=fDUstpamEgq_J~gGHMaPRg xclbin Information - xclbin Information - 2021.2 English - UG1393 Generated by: v++ (2020.1) on Mon Apr 13 20:19:40 MDT 2020 Version: 2.6.436 Kernels: CopyKernel Signature: Content: Bitstream UUID (xclbin):... information english https://docs.amd.com/r/2023.1-English/ug1393-vitis-application-acceleration/profile-Options?contentId=1F6PueTlrM4nWoSMz764Aw --profile Options - --profile Options - 2023.1 English - UG1393 As discussed in Enabling Profiling in Your Application, there are a number of --profile options that let you enable profiling of the application and kernel... profile options english https://docs.amd.com/r/2023.2-English/ug1393-vitis-application-acceleration/SW-Controllable-Kernels?contentId=0pc2~NwtVViuBqacQATDaA SW-Controllable Kernels - SW-Controllable Kernels - 2023.2 English - UG1393 Software controllable kernels expose a programmable register interface, allowing a host software application to interact with kernels through register reads... sw controllable kernels english https://docs.amd.com/r/2021.2-English/ug1393-vitis-application-acceleration/Adding-C-Models-to-RTL-Kernels?contentId=76HLsuwtXvfmUor7UMLzhA Adding C-Models to RTL Kernels - Adding C-Models to RTL Kernels - 2021.2 English - UG1393 RTL kernels support the hardware emulation build, and the hardware build described in Build Targets, but an RTL kernel in its native form does not support... adding c models rtl kernels https://docs.amd.com/r/2023.2-English/ug1393-vitis-application-acceleration/Sub-Buffers?contentId=eKC9jI0YmyFG8V5PJXhoUw Sub-Buffers - Sub-Buffers - 2023.2 English - UG1393 Though not very common, using sub-buffers can be very useful in specific situations. The following sections discuss the scenarios where using sub-buffers can... sub buffers english https://docs.amd.com/r/2023.2-English/ug1393-vitis-application-acceleration/VPP_ACC-Class-API?contentId=SJTJEEaRRVk_35MWIBY_bQ VPP_ACC Class API - VPP_ACC Class API - 2023.2 English - UG1393 You can define a hardware accelerator derived from the VPP_ACC base class, and build the hardware and software interface with VSC. This section describes the... vpp acc class api english https://docs.amd.com/r/2022.1-English/ug1393-vitis-application-acceleration/Measure-Running-Time?contentId=9KdgVanYtu8E5XPdTVCDkQ Measure Running Time - Measure Running Time - 2022.1 English - UG1393 Measuring running time is a standard practice in software development. This can be done using common software profiling tools such as gprof, or by... running time measure english https://docs.amd.com/r/2022.1-English/ug1393-vitis-application-acceleration/RTL-Kernel-Development-Flow?contentId=8jfZOm~vPCoYrI~_oN7HsA RTL Kernel Development Flow - RTL Kernel Development Flow - 2022.1 English - UG1393 This section explains the process of creating RTL kernels using the Package IP feature inside the Vivado Design Suite. The Package IP command provides a... kernel development rtl flow english https://docs.amd.com/r/2022.2-English/ug1393-vitis-application-acceleration/Accelerator-Execution-Models?contentId=mPQyeQ1WCv73aOMskLDTLQ Accelerator Execution Models - Accelerator Execution Models - 2022.2 English - UG1393 The following sections describe various styles of accelerator execution models. Each one is uniquely defines a system architecture that may used for an... execution models accelerator english https://docs.amd.com/r/2022.2-English/ug1393-vitis-application-acceleration/Creating-Multiple-Compute-Units?contentId=jAmoD7eKI9wIabu2zw2D3g Creating Multiple Compute Units - Creating Multiple Compute Units - 2022.2 English - UG1393 When building the .xclbin file you can specify the number of kernel instances, or compute units (CU) to implement into the hardware by using the... compute units creating multiple english https://docs.amd.com/r/2023.2-English/ug1393-vitis-application-acceleration/Executing-Commands-on-the-FPGA Executing Commands on the FPGA - Executing Commands on the FPGA - 2023.2 English - UG1393 Once the OpenCL environment is initialized, the host application is ready to issue commands to the device and interact with the kernels. These commands... executing commands on the fpga english https://docs.amd.com/r/2023.2-English/ug1393-vitis-application-acceleration/syn.directive.loop_tripcount?contentId=UFlrxKaQBbcUMxNPUC1iBg syn.directive.loop_tripcount - syn.directive.loop_tripcount - 2023.2 English - UG1393 Description The loop tripcount is the total number of iterations performed by a loop. Vitis HLS reports the total latency of each loop (the number of cycles to... syn directive loop english https://docs.amd.com/r/2022.2-English/ug1393-vitis-application-acceleration/Measure-Running-Time?contentId=J6xUkMP1BAeQ4LcUk~PQQQ Measure Running Time - Measure Running Time - 2022.2 English - UG1393 Measuring running time is a standard practice in software development. This can be done using common software profiling tools such as gprof, or by... running time measure english https://docs.amd.com/r/2022.2-English/ug1393-vitis-application-acceleration/Using-the-RTL-Kernel-Wizard?contentId=dEaQj7I~q~4_h6xuaxdlMw Using the RTL Kernel Wizard - Using the RTL Kernel Wizard - 2022.2 English - UG1393 The RTL Kernel wizard is organized into multiple pages that break down the process of defining an RTL kernel. The pages of the wizard include: General Settings... using rtl kernel wizard english https://docs.amd.com/r/2023.2-English/ug1393-vitis-application-acceleration/Compile-Options?contentId=TdjmKx5szdQb_GSnY3brvg Compile Options - Compile Options - 2023.2 English - UG1393 The syn.compile commands specify the default behavior for compilation of the HLS component. syn.compile.design_size_max_warning Specifies the design size that... compile options english https://docs.amd.com/r/2021.2-English/ug1393-vitis-application-acceleration/scan-xbmgmt?contentId=pQMnoYAkhr8Geef~qqyrWQ scan (xbmgmt) - scan (xbmgmt) - 2021.2 English - UG1393 Important: This option cannot be used with embedded processor platforms. The xbmgmt scan command returns a list of all the detected management PCIe functions.... scan english https://docs.amd.com/r/2023.2-English/ug1393-vitis-application-acceleration/Getting-Started-with-Vitis?contentId=FhPLXgGWvxUQbGxr8pfOmQ Getting Started with Vitis - Getting Started with Vitis - 2023.2 English - UG1393 This section contains the following chapters: Navigating Content by Design Process Vitis Software Platform Release Notes Installation getting started with vitis english https://docs.amd.com/r/2023.2-English/ug1393-vitis-application-acceleration/A-Sample-Application?contentId=rln0Dh14fSv1oUGJndHzBA A Sample Application - A Sample Application - 2023.2 English - UG1393 This section provides a snapshot of the evolution of a program written for CPU into an application written for FPGA-based acceleration. This section is... a sample application english https://docs.amd.com/r/2022.1-English/ug1393-vitis-application-acceleration/Eliminate-I/O-Contentions?contentId=LHZ5q1MlCRkUMJjKlE3NDA Eliminate I/O Contentions - Eliminate I/O Contentions - 2022.1 English - UG1393 I/O contentions appear when a given I/O port of internal memory resources must be accessed more than once per loop iteration. A loop cannot be pipelined with... eliminate contentions english https://docs.amd.com/r/2022.2-English/ug1393-vitis-application-acceleration/Simulator-Support Simulator Support - Simulator Support - 2022.2 English - UG1393 The Vitis tool uses the Vivado logic simulator (xsim) as the default simulator for all platforms, including Alveo Data Center accelerator cards, and Versal and... simulator support english https://docs.amd.com/r/2023.2-English/ug1393-vitis-application-acceleration/Developing-Applications Developing Applications - Developing Applications - 2023.2 English - UG1393 This section contains the following chapters: Programming Model describes the elements of the Vitis development environment Writing the Software Application... developing applications english https://docs.amd.com/r/2021.2-English/ug1393-vitis-application-acceleration/Interface-Information Interface Information - Interface Information - 2021.2 English - UG1393 The following shows the reported PCIe interface information. Interface Name: PCIe Interface Type: gen3x16 PCIe Vendor Id: 0x10EE PCIe Device Id: 0x5000 PCIe... interface information english https://docs.amd.com/r/2022.2-English/ug1393-vitis-application-acceleration/Revision-History?contentId=ajfeHnCyV53xirfJPeAukg Revision History - Revision History - 2022.2 English - UG1393 Getting Started with Vitis Revision History The following table shows the revision history for Getting Started with Vitis. Section Revision Summary 12/7/2022... revision history english https://docs.amd.com/r/2023.2-English/ug1393-vitis-application-acceleration/Keep-the-Device-Kernels-Utilized?contentId=ax3zr4kBnXVMHad6aElLLA Keep the Device Kernels Utilized - Keep the Device Kernels Utilized - 2023.2 English - UG1393 Kernels might be present in the device, but they will only run when the application requests them. To maximize performance, engineer the application so that it... the device keep kernels utilized english https://docs.amd.com/r/2023.2-English/ug1393-vitis-application-acceleration/General-Purpose-Python-API?contentId=HM52S3hrJqnv63p~mqg_vQ General Purpose Python API - General Purpose Python API - 2023.2 English - UG1393 Here is the list of general purpose APIs that can be used with custom user-defined datatypes. With these API you can send and receive data in the form of... general purpose python api english https://docs.amd.com/r/2021.2-English/ug1393-vitis-application-acceleration/Platform Platform - Platform - 2021.2 English - UG1393 Upon initialization, the host application needs to identify a platform composed of one or more Xilinx devices. The following code fragment shows a common... platform english https://docs.amd.com/r/2022.1-English/ug1393-vitis-application-acceleration/Profiling-of-C-Code?contentId=oKG3GpR3wybfEFNpQI6Mdg Profiling of C Code - Profiling of C Code - 2022.1 English - UG1393 For C code the provided functions are: xrtURStart() This function establishes the start time of a measured range of activity with the specified ID. The... c code profiling english https://docs.amd.com/r/2023.1-English/ug1393-vitis-application-acceleration/Generate-XSA-file?contentId=1BP92MSXHrDAoBdc11mT_A Generate XSA file - Generate XSA file - 2023.1 English - UG1393 Leverage CED example design to create hardware platform and export XSA file. Add hardware interface based on fixed platform and export XSA file. generate xsa file english https://docs.amd.com/r/2022.1-English/ug1393-vitis-application-acceleration/CU-Cluster-and-Multi-Card-Support?contentId=2MFXDeY3~XEbAjiVaSNwLA CU Cluster and Multi-Card Support - CU Cluster and Multi-Card Support - 2022.1 English - UG1393 If a host machine has only one accelerator card installed, VSC will try to use that card. There will be a fatal error if the card does not match the platform... multi card cu cluster support english https://docs.amd.com/r/2021.2-English/ug1393-vitis-application-acceleration/Vitis-Hardware-Function-Settings?contentId=~3nNfIawqIqCQiRunRLnag Vitis Hardware Function Settings - Vitis Hardware Function Settings - 2021.2 English - UG1393 To edit the settings for the hardware functions, expand the build target for the kernels project in the Assistant view, select the hardware function, and click... vitis hardware function settings english https://docs.amd.com/r/2022.1-English/ug1393-vitis-application-acceleration/Creating-an-Archive-File?contentId=nTiEENq140OFzq7aCWoNcg Creating an Archive File - Creating an Archive File - 2022.1 English - UG1393 At times while developing your project, you might introduce changes in your host or kernel code that completely alters the contents or quality of the various... an archive creating file english https://docs.amd.com/r/2022.2-English/ug1393-vitis-application-acceleration/Eliminate-I/O-Contentions Eliminate I/O Contentions - Eliminate I/O Contentions - 2022.2 English - UG1393 I/O contentions appear when a given I/O port of internal memory resources must be accessed more than once per loop iteration. A loop cannot be pipelined with... eliminate contentions english https://docs.amd.com/r/2022.2-English/ug1393-vitis-application-acceleration/PROFILE_PORT-Examples?contentId=EJAtj6MMYwFXNfrkXN2mkQ PROFILE_PORT Examples - PROFILE_PORT Examples - 2022.2 English - UG1393 To enable profiling for all ports of all kernels: PROFILE_PORT("all"); To enable profiling for all ports of hls_kernel function on compute unit 0 and 2:... profile port examples english https://docs.amd.com/r/2023.1-English/ug1393-vitis-application-acceleration/Scalars Scalars - Scalars - 2023.1 English - UG1393 Scalar arguments are used to pass control type information to the kernels. Scalar arguments cannot be read back from the host. For each argument that is... scalars english https://docs.amd.com/r/2022.1-English/ug1393-vitis-application-acceleration/API/Pseudo-Code API/Pseudo Code - API/Pseudo Code - 2022.1 English - UG1393 For API/pseudo code, a single instance of AXI4 memory map transaction is used for the complete transaction. This is in line with how payload is used in the... pseudo code api english https://docs.amd.com/r/2020.2-English/ug1393-vitis-application-acceleration/Diff-Two-Text-Files Diff Two Text Files - Diff Two Text Files - 2020.2 English - UG1393 The Vitis analyzer lets you compare two reports of the same type. This opens a report window similar to the one shown below. Figure 1. Compare Text Files The... text files diff two english https://docs.amd.com/r/2023.1-English/ug1393-vitis-application-acceleration/HLS-Synthesis-Report?contentId=N1KE5BggfQarFCOe0w4Rjw HLS Synthesis Report - HLS Synthesis Report - 2023.1 English - UG1393 The HLS report provides details about the high-level synthesis (HLS) process of a user kernel and is generated during the compilation process for hardware... synthesis report hls english https://docs.amd.com/r/2023.1-English/ug1393-vitis-application-acceleration/Design-Capture-and-Modeling Design Capture and Modeling - Design Capture and Modeling - 2023.1 English - UG1393 The previous section described the organization, software interfaces, and hardware compiled by VSC from a unified C++ model. The following is a quick summary... design capture modeling english https://docs.amd.com/r/2022.1-English/ug1393-vitis-application-acceleration/Vitis-IDE-Guidance-View?contentId=qOIFxI0UdHapXPR7DxVzDg Vitis IDE Guidance View - Vitis IDE Guidance View - 2022.1 English - UG1393 After building or running a specific build configuration, the Guidance tab of the Console view displays a list of errors, warnings, and suggestions related to... vitis ide guidance view english https://docs.amd.com/r/2023.1-English/ug1393-vitis-application-acceleration/Vitis-Build-Configuration-Settings?contentId=gce8vboycCjTfWYO8P1tmg Vitis Build Configuration Settings - Vitis Build Configuration Settings - 2023.1 English - UG1393 To edit the settings for any of the build configurations under a project, select the build configuration in the Assistant view and click the Settings button (... build configuration vitis settings english https://docs.amd.com/r/2023.2-English/ug1393-vitis-application-acceleration/Measure-Running-Time?contentId=SGKxqWxRWll62JxCFTRnoQ Measure Running Time - Measure Running Time - 2023.2 English - UG1393 Measuring running time is a standard practice in software development. This can be done using common software profiling tools such as gprof, or by... running time measure english https://docs.amd.com/r/2021.2-English/ug1393-vitis-application-acceleration/SW-Controllable-Kernels SW-Controllable Kernels - SW-Controllable Kernels - 2021.2 English - UG1393 Software controllable kernels expose a programmable register interface, allowing a host software application to interact with kernels through register reads... sw controllable kernels english https://docs.amd.com/r/2023.2-English/ug1393-vitis-application-acceleration/Data-Driven-Kernels?contentId=Dk5q~iK3fUAu5uK63LI60A Data Driven Kernels - Data Driven Kernels - 2023.2 English - UG1393 These kernels are present in the device but are not directly managed by the software application, instead triggered by the arrival of data at the interface.... data driven kernels english https://docs.amd.com/r/2022.2-English/ug1393-vitis-application-acceleration/HLS-Report HLS Report - HLS Report - 2022.2 English - UG1393 The HLS report provides details about the high-level synthesis (HLS) process of a user kernel and is generated during the compilation process for hardware... hls report english https://docs.amd.com/r/2020.2-English/ug1393-vitis-application-acceleration/Quality-of-Results-Considerations Quality of Results Considerations - Quality of Results Considerations - 2020.2 English - UG1393 The following recommendations help improve results for timing and area: Pipeline all reset inputs and internally distribute resets avoiding high fanout nets.... quality results considerations english https://docs.amd.com/r/2021.2-English/ug1393-vitis-application-acceleration/Continuous-Trace-Capture?contentId=6rGqUmiuN~t_A2J0lmvRBQ Continuous Trace Capture - Continuous Trace Capture - 2021.2 English - UG1393 The Vitis tool supports recording continuous trace data while the application is running. The application can run for a very long time thus leading to the... continuous trace capture english https://docs.amd.com/r/2020.2-English/ug1393-vitis-application-acceleration/Step-4-Improve-Loop-Latencies?contentId=OW8UxNYpWz3x8LXO~~WQLA Step 4: Improve Loop Latencies - Step 4: Improve Loop Latencies - 2020.2 English - UG1393 After identifying loops latencies that exceed their target, the first optimization to consider is loop unrolling. step improve loop latencies english https://docs.amd.com/r/2022.2-English/ug1393-vitis-application-acceleration/Getting-Started-with-Vitis?contentId=57Qzmxv263dW8cmrZklfUg Getting Started with Vitis - Getting Started with Vitis - 2022.2 English - UG1393 getting started with vitis english https://docs.amd.com/r/2022.2-English/ug1393-vitis-application-acceleration/Controlling-Report-Generation?contentId=ETpqUN4JuflSzO1oY6F8lg Controlling Report Generation - Controlling Report Generation - 2022.2 English - UG1393 The v++ -R option (or --report_level) controls the level of information to report during compilation or linking for hardware emulation and system targets.... report generation controlling english https://docs.amd.com/r/2022.1-English/ug1393-vitis-application-acceleration/Compiling-and-Linking-for-x86?contentId=WRyZUEheGNQm~2JwLWFwSw Compiling and Linking for x86 - Compiling and Linking for x86 - 2022.1 English - UG1393 Tip: Set up the command shell or window as described in Setting Up the Vitis Environment prior to running the tools. Each source file of the host application... compiling linking english https://docs.amd.com/r/2022.2-English/ug1393-vitis-application-acceleration/Import-a-Vitis-Project?contentId=CYRjCUHni74c_bQeZVzaRQ Import a Vitis Project - Import a Vitis Project - 2022.2 English - UG1393 import vitis project english https://docs.amd.com/r/2023.1-English/ug1393-vitis-application-acceleration/Event-Synchronization?contentId=q2fN3HTYQ8_TNEuURmKfrQ Event Synchronization - Event Synchronization - 2023.1 English - UG1393 All OpenCL enqueue-based API calls are asynchronous. These commands will return immediately after the command is enqueued in the command queue. To pause the... event synchronization english https://docs.amd.com/r/2022.2-English/ug1393-vitis-application-acceleration/RTL-Kernel-XML-File?contentId=MJeNzIDLMiSoKH8uIXPKnw RTL Kernel XML File - RTL Kernel XML File - 2022.2 English - UG1393 Tip: The package_xo command will create a kernel.xml file from the component.xml of a packaged IP, so you do not need to manually provide one, or generate one... xml file rtl kernel english https://docs.amd.com/r/2023.2-English/ug1393-vitis-application-acceleration/Command-to-Clear-the-Session?contentId=R3gSTh5JewpUrqTlLGb_lg Command to Clear the Session - Command to Clear the Session - 2023.2 English - UG1393 The following command is used to clear the session: clear to clear the session command english https://docs.amd.com/r/2023.2-English/ug1393-vitis-application-acceleration/Timeline-Trace?contentId=5xtFwp_EthpEECn71CiC1g Timeline Trace - Timeline Trace - 2023.2 English - UG1393 Profiling also shows a timeline trace for various phases of run in the application layer, as shown in the picture. This is presented under the "SystemCompile"... timeline trace english https://docs.amd.com/r/2022.2-English/ug1393-vitis-application-acceleration/package-Options?contentId=cfPyu~E40d5dWDhNDILAPw --package Options - --package Options - 2022.2 English - UG1393 Introduction As described in Packaging the System, the v++ --package, or -p step, generates and packages the final product at the end of the v++ compile and... package options english https://docs.amd.com/r/2021.2-English/ug1393-vitis-application-acceleration/Timeline-Trace?contentId=O9TJxTnjuQdSNTwh8fBERA Timeline Trace - Timeline Trace - 2021.2 English - UG1393 The Timeline Trace collects and displays host and kernel events on a common timeline to help you understand and visualize the overall health and performance of... timeline trace english https://docs.amd.com/r/2022.2-English/ug1393-vitis-application-acceleration/Terminology?contentId=QTA9FFmvEcjTN7ARsAgI9Q Terminology - Terminology - 2022.2 English - UG1393 PL or Programmable Logic The part of the FPGA that is made of fundamental programmable building blocks such as flip-flops registers, look-up-tables (LUTs),... terminology english https://docs.amd.com/r/2020.2-English/ug1393-vitis-application-acceleration/Kernel-Execution Kernel Execution - Kernel Execution - 2020.2 English - UG1393 Often the compute intensive task required by the host application can be defined inside a single kernel, and the kernel is executed only once to work on the... kernel execution english https://docs.amd.com/r/2022.1-English/ug1393-vitis-application-acceleration/Software-Emulation?contentId=J_TDfQgt9~0GkdoLf813Xg Software Emulation - Software Emulation - 2022.1 English - UG1393 VSC uses a single source C++ model which can be functionally validated fast. The software emulation target (-t sw_emu) must be specified during v++ compile... software emulation english https://docs.amd.com/r/2020.2-English/ug1393-vitis-application-acceleration/Automated-Setup-for-Hardware-Debug Automated Setup for Hardware Debug - Automated Setup for Hardware Debug - 2020.2 English - UG1393 Set up your Vitis core development kit as described in Setting Up the Vitis Environment. Use the debug_hw script to launch the xvc_pcie and hw_server apps as... automated setup hardware debug english https://docs.amd.com/r/2021.2-English/ug1393-vitis-application-acceleration/Executing-Kernels-on-the-Device Executing Kernels on the Device - Executing Kernels on the Device - 2021.2 English - UG1393 The execution of a kernel is associated with a class called xrt::run that implements methods to start and wait for kernel execution. Most interaction with... on the executing kernels device english https://docs.amd.com/r/2020.2-English/ug1393-vitis-application-acceleration/mem-write?contentId=5epjXck5PSJUzXca8U3rBQ mem --write - mem --write - 2020.2 English - UG1393 Important: This option cannot be used with embedded processor platforms. The mem --write command writes a defined pattern to a specified set of memory... mem write english https://docs.amd.com/r/2023.1-English/ug1393-vitis-application-acceleration/Step-5-Improve-Loop-Throughput Step 5: Improve Loop Throughput - Step 5: Improve Loop Throughput - 2023.1 English - UG1393 If improving loop latency by reducing the trip count was not sufficient, look at ways to reduce the initiation interval (II). The loop II is the count of clock... step improve loop throughput english https://docs.amd.com/r/2023.2-English/ug1393-vitis-application-acceleration/Kernel-Interface-Requirements?contentId=WWBNfbcmlmSlB6JLTwGvpw Kernel Interface Requirements - Kernel Interface Requirements - 2023.2 English - UG1393 To enable the Vitis compiler to connect kernels into the target platform, an RTL kernel must adhere to the requirements described in PL Kernel Properties. The... kernel interface requirements english https://docs.amd.com/r/2022.1-English/ug1393-vitis-application-acceleration/Multiple-Compute-Units?contentId=eJvO6L4WhVRBr5wT~5LY3A Multiple Compute Units - Multiple Compute Units - 2022.1 English - UG1393 Depending on available resources on the target device, multiple compute units of the same kernel (or different kernels) can be created to run in parallel,... compute units multiple english https://docs.amd.com/r/2023.2-English/ug1393-vitis-application-acceleration/Creating-the-XO?contentId=CTFst_L0_VeIaOVZgNLDsw Creating the XO - Creating the XO - 2023.2 English - UG1393 To generate XO file from the SystemC model, use the create_sc_xo command. This takes the SystemC kernel source file as input and creates IP that generates the... the xo creating english https://docs.amd.com/r/2022.2-English/ug1393-vitis-application-acceleration/Memory-Configuration?contentId=bH5Ybuevrhzx3BnwJB3fjA Memory Configuration - Memory Configuration - 2022.2 English - UG1393 Name: bank0 Index: 0 Type: MEM_DDR4 Base Address: 0x0 Address Size: 0x400000000 Bank Used: No Name: bank1 Index: 1 Type: MEM_DDR4 Base Address: 0x400000000... memory configuration english https://docs.amd.com/r/2022.2-English/ug1393-vitis-application-acceleration/Platform-Types?contentId=ryzfo1uNemeFXOqGnHZ7kQ Platform Types - Platform Types - 2022.2 English - UG1393 The Vitis target platforms can be customized with unique hardware and software components. There are two general types of platforms: fixed platforms and... platform types english https://docs.amd.com/r/2023.2-English/ug1393-vitis-application-acceleration/syn.directive.array_reshape?contentId=QQZcSg64y2aLPkclu4fZGQ syn.directive.array_reshape - syn.directive.array_reshape - 2023.2 English - UG1393 Description Important: syn.directive.array_partition and syn.directive.array_reshape are not supported for M_AXI Interfaces on the top-level function. Instead... syn directive array reshape english https://docs.amd.com/r/2022.1-English/ug1393-vitis-application-acceleration/Using-the-Standalone-Debug-Flow?contentId=jYl2WUhKyImEUz3Qy81H~A Using the Standalone Debug Flow - Using the Standalone Debug Flow - 2022.1 English - UG1393 The Vitis IDE lets you open the debug tool for projects that have been built using the command line flow. Launching Standalone Debug for Embedded Platforms The... using standalone debug flow english https://docs.amd.com/r/2023.2-English/ug1393-vitis-application-acceleration/Command-to-Display-History?contentId=jOJiA6my493siHqsACti~A Command to Display History - Command to Display History - 2023.2 English - UG1393 Use history command to print recent input history. Vitis [1]: ls vadd/ logs/ Vitis [2]: history ls history By default, input history is printed without the... command display history english https://docs.amd.com/r/2020.2-English/ug1393-vitis-application-acceleration/opencl_unroll_hint opencl_unroll_hint - opencl_unroll_hint - 2020.2 English - UG1393 Description Important: This is a compiler hint which the compiler can ignore. Loop unrolling is an optimization technique available in the Vitis compiler. The... opencl hint english https://docs.amd.com/r/2023.2-English/ug1393-vitis-application-acceleration/Packaging-Images?contentId=_2gCBZ8z4oCQnexYUCyECA Packaging Images - Packaging Images - 2023.2 English - UG1393 The Vitis compiler (v++) has three stages: -c or --compile to compile acceleration kernels -l or --link to link acceleration kernels with platform logic. -p or... packaging images english https://docs.amd.com/r/2023.2-English/ug1393-vitis-application-acceleration/Buffer-Memory-Segmentation?contentId=HodN8frXug7zzlogiz2ssw Buffer Memory Segmentation - Buffer Memory Segmentation - 2023.2 English - UG1393 Allocation and deallocation of memory buffers can lead to memory segmentation in the DDR controllers. This might result in sub-optimal performance of compute... buffer memory segmentation english https://docs.amd.com/r/2022.1-English/ug1393-vitis-application-acceleration/emconfigutil-Settings emconfigutil Settings - emconfigutil Settings - 2022.1 English - UG1393 Select the emconfigutil command options in the GCC Compiler and Linker Settings dialog box, which you can open from the Build Configuration Settings dialog box... settings english https://docs.amd.com/r/2023.1-English/ug1393-vitis-application-acceleration/Building-Hardware?contentId=xW76sevv5mPOS5hG5i5Rzw Building Hardware - Building Hardware - 2023.1 English - UG1393 This chapter will describe the key aspects of building the accelerator hardware using VSC. The first section describes the user-defined C++ accelerator class... building hardware english https://docs.amd.com/r/2022.1-English/ug1393-vitis-application-acceleration/Vitis-Application-Development-Flow?contentId=hC6iChvu6LjJ~eOZC3pxfA Vitis Application Development Flow - Vitis Application Development Flow - 2022.1 English - UG1393 In this section, you will learn about the Vitis application development flow first and then review a methodology for re-architecting a CPU application for... application development vitis flow english https://docs.amd.com/r/2021.2-English/ug1393-vitis-application-acceleration/advanced-Options?contentId=y5UF9RQBp4yjDiQ8mCp~zA --advanced Options - --advanced Options - 2021.2 English - UG1393 The --advanced.param and --advanced.prop options specify parameters and properties for use by the v++ command. When compiling or linking, these options offer... advanced options english https://docs.amd.com/r/2022.2-English/ug1393-vitis-application-acceleration/Adding-Hardware-Interfaces?contentId=BO9JEyAn3HjrNM0Xg~FrwQ Adding Hardware Interfaces - Adding Hardware Interfaces - 2022.2 English - UG1393 The following table shows the possible Vitis inputs and the minimal requirements for an acceleration embedded platform. Table 1. Available Interfaces for Vitis... hardware interfaces adding english https://docs.amd.com/r/2020.2-English/ug1393-vitis-application-acceleration/vitis-debug-Command-Line vitis -debug Command Line - vitis -debug Command Line - 2020.2 English - UG1393 Command Line Usage The Vitis software platform standalone debug feature lets you launch the Vitis IDE for debugging an existing command line project. In the... command line vitis debug english https://docs.amd.com/r/2021.2-English/ug1393-vitis-application-acceleration/Memory-Mapped-Interfaces?contentId=ehy2aStnP8rrmFwb~MW5PA Memory Mapped Interfaces - Memory Mapped Interfaces - 2021.2 English - UG1393 Memory mapped interfaces are inferred from pointer parameters. They allow kernels to read and write data in global memory, which is the memory that is shared... memory mapped interfaces english https://docs.amd.com/r/2023.2-English/ug1393-vitis-application-acceleration/syn.directive.bind_storage?contentId=8wdt64_kpavJd6FmctKmxg syn.directive.bind_storage - syn.directive.bind_storage - 2023.2 English - UG1393 Description Vitis HLS assigns arrays in the code using specific memory resources (or types). The tool automatically determines the resource to use.... syn directive bind storage english https://docs.amd.com/r/2022.1-English/ug1393-vitis-application-acceleration/Enabling-Low-Overhead-Profiling?contentId=7UrguTlzzjrKZuw39EfyDA Enabling Low Overhead Profiling - Enabling Low Overhead Profiling - 2022.1 English - UG1393 The Vitis software platform supports low overhead profiling that provides minimal information with little effect on execution time. Using this option during... enabling low overhead profiling english https://docs.amd.com/r/2022.1-English/ug1393-vitis-application-acceleration/package_xo-Command?contentId=WwcUwSg9T40YjvxAT_OfEQ package_xo Command - package_xo Command - 2022.1 English - UG1393 package xo command english https://docs.amd.com/r/2023.2-English/ug1393-vitis-application-acceleration/Utilities-for-Hardware-Debugging?contentId=c41nScO2LkPsbdnv0u3UgA Utilities for Hardware Debugging - Utilities for Hardware Debugging - 2023.2 English - UG1393 In some cases, the normal Vitis IDE and command line debug features are limited in their ability to isolate an issue. This is especially true when the software... utilities hardware debugging english https://docs.amd.com/r/2022.1-English/ug1393-vitis-application-acceleration/Zynq-7000-PS-Arguments-for-QEMU Zynq-7000 PS Arguments for QEMU - Zynq-7000 PS Arguments for QEMU - 2022.1 English - UG1393 Zynq-7000 PS(a9) is emulated by qemu-system-aarch64 QEMU binary. Most common command line switches of PS are captured in qemu_args.txt. Table 1. Zynq-7000... zynq ps arguments qemu english https://docs.amd.com/r/2023.2-English/ug1393-vitis-application-acceleration/syn.directive.occurrence?contentId=8y1~B_Fot3Da0qhD_0JQqg syn.directive.occurrence - syn.directive.occurrence - 2023.2 English - UG1393 Description When pipelining functions or loops, the OCCURRENCE pragma or directive specifies that the code in a pipelined function call within the pipelined... syn directive occurrence english https://docs.amd.com/r/2021.2-English/ug1393-vitis-application-acceleration/Profiling-of-C-Code?contentId=ZEXsl6hAmni5YZk5TuaO9w Profiling of C Code - Profiling of C Code - 2021.2 English - UG1393 For C code the provided functions are: xrtURStart() This function establishes the start time of a measured range of activity with the specified ID. The... c code profiling english https://docs.amd.com/r/2023.1-English/ug1393-vitis-application-acceleration/Latency-Information?contentId=3WKnVR4GU83QjnPqC5gsGQ Latency Information - Latency Information - 2023.1 English - UG1393 The latency information presents the execution profile of each CU in the binary container. When analyzing this data, it is important to recognize that all... latency information english https://docs.amd.com/r/2022.2-English/ug1393-vitis-application-acceleration/Run-Baremetal-Software-Emulation?contentId=4o64cm2SS~rfwKsK7TKEcA Run Baremetal Software Emulation - Run Baremetal Software Emulation - 2022.2 English - UG1393 To step back from creating acceleration applications for platform verification, you can run emulation of baremetal host applications to test the hardware... run baremetal software emulation english