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https://docs.amd.com/r/2021.2-English/ug909-vivado-partial-reconfiguration/Logical-Connectivity-Contents?contentId=6BqroWj2lM3NQkwRC8kctg Logical Connectivity Contents - Logical Connectivity Contents - 2021.2 English - UG909 When the Abstract Shell is created, some static logic is included in the Abstract Shell, based on connectivity. All interface paths to and from the RP, up to... logical connectivity contents english https://docs.amd.com/r/en-US/ug909-vivado-partial-reconfiguration/Modular-NoC-DFX-Tutorials Modular NoC DFX Tutorials - Modular NoC DFX Tutorials - 2025.2 English - UG909 Refer to the modular NoC-based DFX design tutorial posted on GitHub. modular noc dfx tutorials english https://docs.amd.com/r/2020.2-English/ug909-vivado-partial-reconfiguration/Static-Design-Updates Static Design Updates - Static Design Updates - 2020.2 English - UG909 Just as with the standard DFX design flow, implementation results are created in-context from the top down. If any part of the design that is considered static... design updates static english https://docs.amd.com/r/2021.1-English/ug909-vivado-partial-reconfiguration/Configuration-Frames Configuration Frames - Configuration Frames - 2021.1 English - UG909 All user-programmable features inside Xilinx FPGA and SoC devices are controlled by volatile memory cells that must be configured at power-up. These memory... configuration frames english https://docs.amd.com/r/2022.1-English/ug909-vivado-partial-reconfiguration/Editing-Reconfigurable-Modules Editing Reconfigurable Modules - Editing Reconfigurable Modules - 2022.1 English - UG909 After selecting Next to progress past the introduction, the first content page allows you to define new RMs for any Partition Definitions (PD) defined. The... editing modules english https://docs.amd.com/r/2022.1-English/ug909-vivado-partial-reconfiguration/Known-Limitations?contentId=5xuC9Gm7TN0~hwoQb5HORQ Known Limitations - Known Limitations - 2022.1 English - UG909 Certain features are not yet developed or supported in the current release. These include: When selecting Pblock ranges to define the size and shape of the RP,... known limitations english https://docs.amd.com/r/en-US/ug909-vivado-partial-reconfiguration/BLI-Floorplan-Alignment BLI Floorplan Alignment - BLI Floorplan Alignment - 2025.2 English - UG909 In Versal devices, boundary logic interfaces (BLI) tiles are additional register stages available for signals going in and out of programmable logic (PL) to... bli floorplan alignment english https://docs.amd.com/r/2023.2-English/ug909-vivado-partial-reconfiguration/Design-Revision-Checks Design Revision Checks - Design Revision Checks - 2023.2 English - UG909 A partial bitstream contains programming information and little else, as described in Configuring the Device. While you do not need to identify the target... design revision checks english https://docs.amd.com/r/2021.1-English/ug909-vivado-partial-reconfiguration/Abstract-Shell-Design-Flow Abstract Shell Design Flow - Abstract Shell Design Flow - 2021.1 English - UG909 The Abstract Shell design flow is nearly identical to the standard non-project Dynamic Function eXchange design flow. The differences are limited to the steps... design flow abstract shell english https://docs.amd.com/r/2023.1-English/ug909-vivado-partial-reconfiguration/Editing-Reconfigurable-Modules Editing Reconfigurable Modules - Editing Reconfigurable Modules - 2023.1 English - UG909 After selecting Next to progress past the introduction, the first content page allows you to define new RMs for any Partition Definitions (PD) defined. The... editing modules english https://docs.amd.com/r/2022.2-English/ug909-vivado-partial-reconfiguration/Dynamic-Function-eXchange-Commands?contentId=QKm5JTT0WNoOvLmxhfaRng Dynamic Function eXchange Commands - Dynamic Function eXchange Commands - 2022.2 English - UG909 The DFX flows are supported through the non-project batch/Tcl interface (no project based commands), as well as within an RTL-based project flow. Example... dynamic function exchange commands english https://docs.amd.com/r/en-US/ug909-vivado-partial-reconfiguration/Design-Considerations Design Considerations - Design Considerations - 2025.2 English - UG909 The flow to create the initial configuration of the design, establishing the static design results, is no different for Abstract Shell than the standard DFX... design considerations english https://docs.amd.com/r/2021.1-English/ug909-vivado-partial-reconfiguration/Tcl-Commands Tcl Commands - Tcl Commands - 2021.1 English - UG909 Like with most everything within the Vivado IDE, the features and tasks for Dynamic Function eXchange you see are driven behind the scenes by Tcl commands. One... tcl commands english https://docs.amd.com/r/2021.1-English/ug909-vivado-partial-reconfiguration/Using-High-Speed-Transceivers Using High Speed Transceivers - Using High Speed Transceivers - 2021.1 English - UG909 Xilinx high speed transceivers (GTH, GTY) are supported within a RP. As with other reconfigurable site types, the entire PU must be included. For the... high speed using transceivers english https://docs.amd.com/r/en-US/ug909-vivado-partial-reconfiguration/Configuration-Frames Configuration Frames - Configuration Frames - 2025.2 English - UG909 All user-programmable features inside AMD FPGA and SoC devices are controlled by volatile memory cells that must be configured at power-up. These memory cells... configuration frames english https://docs.amd.com/r/2021.2-English/ug909-vivado-partial-reconfiguration/Partition-Pin-Placement Partition Pin Placement - Partition Pin Placement - 2021.2 English - UG909 Each pin of an RP has a partition pin (PartPin). By default the tools automatically place these PartPins inside of the RP Pblock range (which is required). For... partition pin placement english https://docs.amd.com/r/2022.2-English/ug909-vivado-partial-reconfiguration/Black-Boxes?contentId=_qH8mG4vKvUGhK926KAc0Q Black Boxes - Black Boxes - 2022.2 English - UG909 You can implement an RP as a pseudo black box, referred to in Vivado as a greybox. To do this, the RP must be a black box in the static design (either from... black boxes english https://docs.amd.com/r/2022.2-English/ug909-vivado-partial-reconfiguration/Active-Low-Resets-and-Clock-Enables Active-Low Resets and Clock Enables - Active-Low Resets and Clock Enables - 2022.2 English - UG909 In Xilinx 7 series FPGAs, there are no local inverters on control signals (resets or clock enables). The following description uses a reset as the example, but... active low resets clock english https://docs.amd.com/r/2022.2-English/ug909-vivado-partial-reconfiguration/Configuration-Time?contentId=LI6~DAu0EZe65shAUGhcEg Configuration Time - Configuration Time - 2022.2 English - UG909 The speed of configuration is directly related to the size of the partial BIT file and the bandwidth of the configuration port. The different configuration... configuration time english https://docs.amd.com/r/2022.2-English/ug909-vivado-partial-reconfiguration/Implementation?contentId=W1hRjTDdky2rU8_L5ycSOQ Implementation - Implementation - 2022.2 English - UG909 Create as many configurations as necessary to implement all RMs at least once. The first configuration loads in synthesis results for top and the first RM. You... implementation english https://docs.amd.com/r/2023.2-English/ug909-vivado-partial-reconfiguration/Supported-Features?contentId=MYqxKCqgS8Kghe9P88I3Kg Supported Features - Supported Features - 2023.2 English - UG909 Abstract Shell creation and implementation for all UltraScale+ and Versal devices that support DFX Abstract Shell flow support for both IP integrator block... supported features english https://docs.amd.com/r/2022.2-English/ug909-vivado-partial-reconfiguration/Implementing-the-DFX-Design?contentId=FejTc3flcLIErnK4xjhobQ Implementing the DFX Design - Implementing the DFX Design - 2022.2 English - UG909 With all the necessary Configuration Runs defined, the design can be synthesized and implemented. The Flow Navigator can be used to pull through any steps of... implementing dfx design english https://docs.amd.com/r/2022.1-English/ug909-vivado-partial-reconfiguration/Timing-Constraints Timing Constraints - Timing Constraints - 2022.1 English - UG909 Timing constraints for a partially reconfigurable design are similar to timing constraints for a traditional flat design. The primary clocks and I/Os must be... timing constraints english https://docs.amd.com/r/2023.2-English/ug909-vivado-partial-reconfiguration/Verifying-Configurations?contentId=kbN_Dix2PADw9cuT8oUkSQ Verifying Configurations - Verifying Configurations - 2023.2 English - UG909 Once all configurations have been completely placed and routed, a final verification check can be done to validate consistency between these configurations... verifying configurations english https://docs.amd.com/r/2023.2-English/ug909-vivado-partial-reconfiguration/Floorplanning-Design-Rule-Checks?contentId=AIxsBjhn2ExdBZjOimVdWA Floorplanning Design Rule Checks - Floorplanning Design Rule Checks - 2023.2 English - UG909 The floorplanning design rule checks (DRCs) ensure that floorplanning guidelines for DFX designs were followed. DRC violations might be due to unsupported... floorplanning design rule checks english https://docs.amd.com/r/2022.1-English/ug909-vivado-partial-reconfiguration/Partial-BIT-File-Integrity Partial BIT File Integrity - Partial BIT File Integrity - 2022.1 English - UG909 Error detection and recovery of partial BIT files have unique requirements compared to loading a full BIT file. If an error is detected in a full BIT file when... file integrity partial bit english https://docs.amd.com/r/2023.2-English/ug909-vivado-partial-reconfiguration/Software-Flow?contentId=cOjjxn89uCXu5DBECwUDKQ Software Flow - Software Flow - 2023.2 English - UG909 This section describes the basic flow, and gives sample commands to execute this flow. software flow english https://docs.amd.com/r/en-US/ug909-vivado-partial-reconfiguration/Support-Resources Support Resources - Support Resources - 2025.2 English - UG909 For support resources such as Answers, Documentation, Downloads, and Forums, see Support. support resources english https://docs.amd.com/r/en-US/ug909-vivado-partial-reconfiguration/PPLOC-Summary?contentId=Z7Yb0N0nXP2tw8oslUaj5w PPLOC Summary - PPLOC Summary - 2025.2 English - UG909 The PPLOC Summary table shows the partition pin count of each RP and the boundary pin count of each RM associated with each RP. There can be differences in the... summary english https://docs.amd.com/r/2020.2-English/ug909-vivado-partial-reconfiguration/Black-Boxes?contentId=CZbxa_OCwh7W2FSrAhhNKw Black Boxes - Black Boxes - 2020.2 English - UG909 You can implement an RP as a pseudo black box, referred to in Vivado as a greybox. To do this, the RP must be a black box in the static design (either from... black boxes english https://docs.amd.com/r/2021.2-English/ug909-vivado-partial-reconfiguration/Design-Requirements-and-Guidelines Design Requirements and Guidelines - Design Requirements and Guidelines - 2021.2 English - UG909 Dynamic Function eXchange requires the use of Vivado 2013.3 or newer. Partial Reconfiguration (PR) is supported in the ISE Design Suite as well. Use the ISE... requirements and guidelines design english https://docs.amd.com/r/2020.2-English/ug909-vivado-partial-reconfiguration/Synthesis?contentId=AnnfMOD7IoVXpAFDD1aUVg Synthesis - Synthesis - 2020.2 English - UG909 Each module (including Static) needs to be synthesized bottom-up so that a netlist or checkpoint exists for static and each RM. Synthesize the top level:... synthesis english https://docs.amd.com/r/2023.2-English/ug909-vivado-partial-reconfiguration/Expansion-of-CONTAIN_ROUTING-Area Expansion of CONTAIN_ROUTING Area - Expansion of CONTAIN_ROUTING Area - 2023.2 English - UG909 The contained routing requirement of RP Pblocks for UltraScale and UltraScale+ devices has been relaxed to allow for improved routing and timing results.... expansion of contain routing area english https://docs.amd.com/r/2023.2-English/ug909-vivado-partial-reconfiguration/Clearing-Bitstreams?contentId=AV1tBnGo7RmduCzgKMWJdw Clearing Bitstreams - Clearing Bitstreams - 2023.2 English - UG909 Unlike the bitstream types noted above, this type is for UltraScale devices only (UltraScale+ does not have this requirement). A new requirement for this... clearing english https://docs.amd.com/r/en-US/ug909-vivado-partial-reconfiguration/Editing-Configuration-Runs?contentId=FcW0M_It4k7NOV~uTXFOZQ Editing Configuration Runs - Editing Configuration Runs - 2025.2 English - UG909 With all the configurations defined, move to the final screen to manage the configuration runs associated with them. Similar to the configurations themselves,... editing configuration runs english https://docs.amd.com/r/2023.1-English/ug909-vivado-partial-reconfiguration/Top-Down-Flow Top-Down Flow - Top-Down Flow - 2023.1 English - UG909 One way BDCs are introduced is by converting a level of hierarchy. To create a level of hierarchy in an existing BD, select one or more elements (using... top down flow english https://docs.amd.com/r/2023.2-English/ug909-vivado-partial-reconfiguration/Summary Summary - Summary - 2023.2 English - UG909 Run the report_pr_configuration_analysis command early in your design flow, after you have established the logic in each RM but before you finalize the... summary english https://docs.amd.com/r/2021.1-English/ug909-vivado-partial-reconfiguration/Checking-Current-Status Checking Current Status - Checking Current Status - 2021.1 English - UG909 At any point, with a design checkpoint open, you can check the current status of any partition by reporting the properties on that cell. Calling... current status checking english https://docs.amd.com/r/2021.1-English/ug909-vivado-partial-reconfiguration/Creating-Pblocks-for-Versal-Devices Creating Pblocks for Versal Devices - Creating Pblocks for Versal Devices - 2021.1 English - UG909 As part of improvements to the Versal architecture, the smallest unit that can be reconfigured is much smaller than in previous architectures. The minimum... creating versal devices english https://docs.amd.com/r/en-US/ug909-vivado-partial-reconfiguration/Register-Inputs-and-Outputs-of-RMs Register Inputs and Outputs of RMs - Register Inputs and Outputs of RMs - 2025.2 English - UG909 AMD recommends registering inputs and outputs of reconfigurable modules (RMs) in a DFX design for multiple reasons. In the parent implementation, the RM used... inputs and outputs register rms english https://docs.amd.com/r/2020.2-English/ug909-vivado-partial-reconfiguration/Floorplan-in-the-Vivado-IDE Floorplan in the Vivado IDE - Floorplan in the Vivado IDE - 2020.2 English - UG909 The Vivado IDE can be used for planning and visualization tasks. The best example of this is using the Device view to create and modify Pblock constraints for... in the floorplan vivado ide english https://docs.amd.com/r/2022.2-English/ug909-vivado-partial-reconfiguration/Hierarchical-Design-Flows?contentId=3ehx2A44Yq152kFf1VnpVw Hierarchical Design Flows - Hierarchical Design Flows - 2022.2 English - UG909 The Dynamic Function eXchange (DFX) flow is an ideal hierarchical design tool for a top-down in-context use case. The ability to implement the static portion... hierarchical design flows english https://docs.amd.com/r/2020.2-English/ug909-vivado-partial-reconfiguration/Flow-Summary?contentId=ASTWx4WfRWGhnB1GKeLT9g Flow Summary - Flow Summary - 2020.2 English - UG909 The Dynamic Function eXchange Project Flow inserts the key requirements of Dynamic Function eXchange into the existing Vivado project solution, accessible... flow summary english https://docs.amd.com/r/2021.2-English/ug909-vivado-partial-reconfiguration/Supported-Boot-Modes-and-Performance?contentId=oSLzsFTWAJNhG3rRdHGQkg Supported Boot Modes and Performance - Supported Boot Modes and Performance - 2021.2 English - UG909 Any primary or secondary boot modes can be used to deliver partial images. Partial PDI can be fetched from Boot devices, over Ethernet or USB, or from DDR.... supported boot modes performance english https://docs.amd.com/r/2021.1-English/ug909-vivado-partial-reconfiguration/UltraRAM-Behavior UltraRAM Behavior - UltraRAM Behavior - 2021.1 English - UG909 Just as with a full device configuration, UltraRAM memory is initialized to all 0's during partial reconfiguration. There is no user defined INIT attribute and... behavior english https://docs.amd.com/r/2021.2-English/ug909-vivado-partial-reconfiguration/Implementation-Design-Flow?contentId=~uNxGdvOr7EXcjTtuy3jGw Implementation Design Flow - Implementation Design Flow - 2021.2 English - UG909 This section describes the implementation flow using the example from Design Structure. The first design pass contains logic for Top and module A, but... design flow implementation english https://docs.amd.com/r/2023.2-English/ug909-vivado-partial-reconfiguration/BLI-Floorplan-Alignment?contentId=uA3mBm7x8Q001FyJGQ8lfA BLI Floorplan Alignment - BLI Floorplan Alignment - 2023.2 English - UG909 In Versal devices, boundary logic interfaces (BLI) tiles are additional register stages available for signals going in and out of programmable logic (PL) to... bli floorplan alignment english https://docs.amd.com/r/2022.2-English/ug909-vivado-partial-reconfiguration/Reading-Design-Constraints?contentId=PbCHu1tE4R_ecMUK19SzNg Reading Design Constraints - Reading Design Constraints - 2022.2 English - UG909 New constraints can be applied for each configuration at various points in the flow. If an RM is read in as a DCP, then any constraints stored in the DCP are... reading design constraints english https://docs.amd.com/r/2020.2-English/ug909-vivado-partial-reconfiguration/Configuration-Analysis-Report?contentId=UlD7bS8c2U5BJeFHJh4ibw Configuration Analysis Report - Configuration Analysis Report - 2020.2 English - UG909 The Dynamic Function eXchange design flow uses multiple versions of the design that must be implemented through place and route. These different configurations... configuration analysis report english https://docs.amd.com/r/2021.2-English/ug909-vivado-partial-reconfiguration/Versal-Use-Cases?contentId=8rfvi4Vk4xFCRkTnu~_2Xg Versal Use Cases - Versal Use Cases - 2021.2 English - UG909 The unique device structure of Versal ACAP open new opportunities for dynamic reconfiguration and related solutions. Versal-specific use cases are listed in... use cases versal english https://docs.amd.com/r/2020.2-English/ug909-vivado-partial-reconfiguration/Bitstream-Generation?contentId=gFVNJjA7T3L1O5q_eb9H~A Bitstream Generation - Bitstream Generation - 2020.2 English - UG909 As in a flat flow, bitstreams are created with the write_bitstream command. For each design configuration, simply issue write_bitstream to create a full... bitstream generation english https://docs.amd.com/r/2021.2-English/ug909-vivado-partial-reconfiguration/References References - References - 2021.2 English - UG909 Vivado Design Suite Tutorial: Dynamic Function eXchange (UG947) Dynamic Function eXchange Controller IP LogiCORE IP Product Guide (PG374) Dynamic Function... references english https://docs.amd.com/r/2020.2-English/ug909-vivado-partial-reconfiguration/Supported-Features?contentId=3ZYvOBwuPHfC5Ybcq3HppA Supported Features - Supported Features - 2020.2 English - UG909 Abstract Shell creation for all UltraScale+ devices Implementation of any RM within an Abstract Shell for a given RP Validation of an implemented RM within an... supported features english https://docs.amd.com/r/2020.2-English/ug909-vivado-partial-reconfiguration/Configuration-Modes?contentId=x0Gzouh4jP~dyUgjyIzNsw Configuration Modes - Configuration Modes - 2020.2 English - UG909 Dynamic Function eXchange is supported using the following configuration modes: ICAP A good choice for user configuration solutions. Requires the creation of... configuration modes english https://docs.amd.com/r/2022.2-English/ug909-vivado-partial-reconfiguration/Design-Hierarchy?contentId=Ex3axUEwGzLtvPQBd4tP_Q Design Hierarchy - Design Hierarchy - 2022.2 English - UG909 Good hierarchical design practices resolve many complexities and difficulties when implementing a partially reconfigurable FPGA design. A clear design instance... design hierarchy english https://docs.amd.com/r/2020.2-English/ug909-vivado-partial-reconfiguration/Dynamic-Function-eXchange-Licensing?contentId=FcfK5W1loAPnSDGxzYLKnA Dynamic Function eXchange Licensing - Dynamic Function eXchange Licensing - 2020.2 English - UG909 Dynamic Function eXchange is available as a feature within the Vivado Design Suite. Starting withVivado 2019.1, no specific license code is necessary to use... dynamic function exchange licensing english https://docs.amd.com/r/2023.1-English/ug909-vivado-partial-reconfiguration/Partial-BIT-File-Integrity?contentId=abYrHrQ7oUGeHILWX~RZHg Partial BIT File Integrity - Partial BIT File Integrity - 2023.1 English - UG909 Error detection and recovery of partial BIT files have unique requirements compared to loading a full BIT file. If an error is detected in a full BIT file when... file integrity partial bit english https://docs.amd.com/r/2022.1-English/ug909-vivado-partial-reconfiguration/Creating-Pblocks-for-Versal-Devices Creating Pblocks for Versal Devices - Creating Pblocks for Versal Devices - 2022.1 English - UG909 As part of improvements to the Versal architecture, the smallest unit that can be reconfigured is much smaller than in previous architectures. The minimum... creating versal devices english