Robuta

https://www.chipsalliance.org/news/progress-in-open-source-systemverilog-uvm-support-in-verilator/

Progress in open source SystemVerilog / UVM support in Verilator | CHIPS Alliance

open source progress uvm support verilator

https://antmicro.com/blog/2023/10/running-simple-uvm-testbenches-in-verilator/

Antmicro · Initial open source support for UVM testbenches in Verilator

open source support initial uvm

https://www.chipsalliance.org/news/constrained-randomization-verilator/

Constrained randomization in Verilator | CHIPS Alliance

verilator chips alliance

https://antmicro.com/blog/2025/07/power-estimation-in-openroad-using-saif-in-verilator/

Antmicro · Power estimation in OpenROAD using SAIF in Verilator

power estimation using verilator

https://antmicro.com/blog/2025/11/bazel-rules-for-renode/

Antmicro · Renode Bazel rules for advanced co-simulation scenarios using Verilator as an example

bazel rules advanced co simulation

https://antmicro.com/blog/2024/09/open-source-uvm-verification-axi-in-verilator/

Antmicro · Enabling open source UVM verification of AXI-based systems in Verilator

open source enabling uvm verification axi

https://www.chipsalliance.org/news/analyze-verilator-processes/

Analyze Verilator processes and ASTs with the astsee suite | CHIPS Alliance

analyze verilator processes suite chips

https://antmicro.com/blog/2024/08/constrained-randomization-in-verilator-implementation-details/

Antmicro · Constrained randomization in Verilator: SystemVerilog constraint to SMT-LIB2 conversion

verilator constraint smt

https://antmicro.com/blog/2025/10/support-for-upstream-uvm-2017-in-verilator/

Antmicro · Support for upstream UVM 2017 in Verilator

support upstream uvm verilator

https://antmicro.com/blog/2025/08/enhancing-coverage-reporting-in-verilator/

Antmicro · Enhancing RTL coverage reporting in Verilator with new features and computation...

enhancing rtl coverage reporting verilator

https://www.chipsalliance.org/news/initial-assertion-control-support-in-verilator/

Initial assertion control support in Verilator | CHIPS Alliance

initial assertion control support verilator

https://antmicro.com/blog/2024/01/analyze-verilator-processes-and-asts/

Antmicro · Analyze Verilator processes and ASTs with the astsee suite

analyze verilator processes