https://www.fpgarelated.com/showarticle/216/vhdl-tutorial-combining-clocked-and-sequential-logic.php
VHDL tutorial - part 2 - Testbench - Gene Breniman
VHDL testbench tutorial for Xilinx ISE showing clock generation, reset sequencing, register strobe writes to select ADC clock rates, plus debugging tips.
vhdl tutorialparttestbenchgene
https://www.embeddedrelated.com/showarticle/262/vhdl-tutorial-combining-clocked-and-sequential-logic.php
VHDL tutorial - A practical example - part 1 - Hardware - Gene Breniman
Hardware walkthrough for a CPLD-based low-power data-acquisition engine, covering components, interfaces, pin assignments, and power choices.
a practical examplevhdl tutorialparthardwaregene
https://www.embeddedrelated.com/showabstract/237.php
VHDL tutorial - A practical example - part 3 - VHDL testbench
VHDL tutorial - A practical example - part 3 - VHDL testbench: Gene Breniman shows how to build self-checking VHDL testbenches and simulate CPLD designs.
a practical examplevhdl tutorialparttestbench
https://www.fpgarelated.com/showarticle/216/vhdl-tutorial-combining-clocked-and-sequential-logic.php
VHDL tutorial - part 2 - Testbench - Gene Breniman
VHDL testbench tutorial for Xilinx ISE showing clock generation, reset sequencing, register strobe writes to select ADC clock rates, plus debugging tips.
vhdl tutorialparttestbenchgene
https://www.embeddedrelated.com/showarticle/262/vhdl-tutorial-combining-clocked-and-sequential-logic.php
VHDL tutorial - A practical example - part 1 - Hardware - Gene Breniman
Hardware walkthrough for a CPLD-based low-power data-acquisition engine, covering components, interfaces, pin assignments, and power choices.
a practical examplevhdl tutorialparthardwaregene