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Stefan Hajnoczi: Building a virtio-serial FPGA device (Part 2): MMIO registers, DMA, and interrupts
This is the second post in a series about building a virtio-serial device in Verilog for an FPGA development board. This time we
stefan hajnoczi buildingvirtio serial fpgadevice part2registers
https://gitlab.com/stefanha/virtio-serial-fpga
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Stefan Hajnoczi: March 2022
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https://blog.vmsplice.net/2026/01/building-virtio-serial-fpga-device-part_01938158793.html
Stefan Hajnoczi: Building a virtio-serial FPGA device (Part 3): virtio-serial device design
This is the third post in a series about building a virtio-serial device in Verilog for an FPGA development board. This time we
stefan hajnoczi buildingvirtio serial fpgapart 3 designdevice
https://gitlab.com/stefanha/virtio-serial-fpga-picorv32/-/blob/main/picosoc/uart_reader.v
picosoc/uart_reader.v · main · Stefan Hajnoczi / virtio-serial-fpga-picorv32 · GitLab
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Stefan Hajnoczi: 2022
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Stefan Hajnoczi: internals
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https://blog.vmsplice.net/2022/04/
Stefan Hajnoczi: April 2022
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Stefan Hajnoczi: September 2021
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Stefan Hajnoczi: 2025
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Stefan Hajnoczi: April 2013
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https://blog.vmsplice.net/2021/01/
Stefan Hajnoczi: January 2021
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Stefan Hajnoczi: April 2019
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Stefan Hajnoczi: December 2025
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Stefan Hajnoczi: May 2020
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https://blog.vmsplice.net/2026/01/building-virtio-serial-fpga-device-part_01060935865.html
Stefan Hajnoczi: Building a virtio-serial FPGA device (Part 4): Virtqueue processing
This is the fourth post in a series about building a virtio-serial device in Verilog for an FPGA development board. This time we
stefan hajnoczi buildingvirtio serial fpgadevice part4processing
https://blog.vmsplice.net/2026/01/building-virtio-serial-fpga-device-part.html
Stefan Hajnoczi: Building a virtio-serial FPGA device (Part 1): Overview
This is a the first post in a series about building a virtio-serial device in Verilog for a Field Programmable Gate Array (FPGA) developme...
stefan hajnoczi buildingvirtio serial fpgadevice part 1overview
https://blog.vmsplice.net/2022/06/
Stefan Hajnoczi: June 2022
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Stefan Hajnoczi: December 2017
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Stefan Hajnoczi: fpga
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https://blog.vmsplice.net/2026/01/building-virtio-serial-fpga-device-part_01486670629.html
Stefan Hajnoczi: Building a virtio-serial FPGA device (Part 6): Writing the RISC-V firmware
This is the final post in a series about building a virtio-serial device in Verilog for an FPGA development board. This time we
stefan hajnoczi buildingvirtio serial fpgadevice part6 writingrisc
https://blog.vmsplice.net/2017/02/
Stefan Hajnoczi: February 2017
Open source and virtualization blog
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