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https://docs.amd.com/r/en-US/ug994-vivado-ip-subsystems/Cutting-and-Pasting?contentId=ewHzzwNS0lcS5I8mAGvyOQ Cutting and Pasting - Cutting and Pasting - 2025.2 English - UG994 You can use Ctrl+C and Ctrl+V to copy and paste blocks in a diagram. This lets you quickly copy IP blocks that are customized, or copy the IP into new... cutting and pasting english https://docs.amd.com/r/2023.2-English/ug994-vivado-ip-subsystems/Standalone-GT?contentId=Q0GqrrFwRjTPYiXhHw90ow Standalone GT - Standalone GT - 2023.2 English - UG994 Design entry for custom IP that connects to GT Quads is through the Bridge IP, which allows you to configure Transceivers Wizard parameters. Use block... standalone gt english https://docs.amd.com/r/2023.2-English/ug994-vivado-ip-subsystems/Working-with-Block-Designs Working with Block Designs - Working with Block Designs - 2023.2 English - UG994 At this point, you should know how to create a block design (BD), populate it with IP, make connections, assign memory address spaces, and validate the design.... working with block designs english https://docs.amd.com/r/2023.1-English/ug994-vivado-ip-subsystems/Debugging-IP-Integrator-Designs?contentId=xGS9kYEwOtnsz~sGGM7uMQ Debugging IP Integrator Designs - Debugging IP Integrator Designs - 2023.1 English - UG994 In-system debugging lets you debug your design in real-time on your target hardware. This is an essential step in design completion. Invariably, one comes... debugging ip integrator designs english https://docs.amd.com/r/en-US/ug994-vivado-ip-subsystems/Adding-Existing-Block-Designs Adding Existing Block Designs - Adding Existing Block Designs - 2025.2 English - UG994 You can add an existing BD as a design source to a new project, either from an existing project or from a remote directory location. Assuming that a BD was... adding existing block designs english https://docs.amd.com/r/2023.1-English/ug994-vivado-ip-subsystems/Non-Project-Script?contentId=JdUFTguYmGenVxftjlHTdA Non-Project Script - Non-Project Script - 2023.1 English - UG994 The following is a sample script for creating a block design in non-project mode. #Set the target part, target language, and board part set_part... non project script english https://docs.amd.com/r/2020.2-English/ug994-vivado-ip-subsystems/Apertures?contentId=1O2LSvZw0kHpt6HWgN~R~A Apertures - Apertures - 2020.2 English - UG994 Apertures are important in address assignment. As stated in the terminology section, an aperture is an offset and range that restricts where a slave segment... apertures english https://docs.amd.com/r/en-US/ug994-vivado-ip-subsystems/Re-Arranging-the-Design-Canvas Re-Arranging the Design Canvas - Re-Arranging the Design Canvas - 2025.2 English - UG994 You can re-arrange IP blocks on the canvas to get a better layout of the BD, and connections between blocks. To arrange a completed diagram or a diagram in... the design arranging canvas english https://docs.amd.com/r/2022.1-English/ug994-vivado-ip-subsystems/Scale-and-Zoom?contentId=Gf0FS6xIcxfyFszQYS1w_Q Scale and Zoom - Scale and Zoom - 2022.1 English - UG994 Slaves can be shown using three scale options: log, linear, and constant size. Figure 1. Scale Options The default is a log scale, where the vertical size of... scale zoom english https://docs.amd.com/r/2023.1-English/ug994-vivado-ip-subsystems/Common-Internal-Bus-Interfaces?contentId=scCrR8LFdL77Z5kWy7laKg Common Internal Bus Interfaces - Common Internal Bus Interfaces - 2023.1 English - UG994 Some common examples of bus interfaces are buses that conform to the AXI specification such as AXI4, AXI4-Lite, andAXI4-Stream. The AXIMM interface includes... bus interfaces common internal english https://docs.amd.com/r/en-US/ug994-vivado-ip-subsystems/Inline-HDL Inline HDL - Inline HDL - 2025.2 English - UG994 IP integrator offers you a variety of useful utility IPs that you can use to create your own designs. You can use both packaged and utility IP's as HDL... inline hdl english https://docs.amd.com/r/2023.2-English/ug994-vivado-ip-subsystems/Packaging-a-Block-Design?contentId=m6mDXzVU5CVvWvOSKdxokw Packaging a Block Design - Packaging a Block Design - 2023.2 English - UG994 When you have created an IP integrator BD, implemented it, validated it, and tested it on the target hardware, and you are satisfied with the functionality of... a block packaging design english https://docs.amd.com/r/2023.1-English/ug994-vivado-ip-subsystems/Cutting-and-Pasting?contentId=h2cBgf36JRGWa3yyZ_WMAA Cutting and Pasting - Cutting and Pasting - 2023.1 English - UG994 You can use Ctrl+C and Ctrl+V to copy and paste blocks in a diagram. This lets you quickly copy IP blocks that have been customized, or copy IP into new... cutting and pasting english https://docs.amd.com/r/2023.1-English/ug994-vivado-ip-subsystems/GT-to-CPM-Integration GT to CPM Integration - GT to CPM Integration - 2023.1 English - UG994 The CPM controller configuration, including GT selection, is handled through the CIPS IP. For information, see the Versal Adaptive SoC CPM Mode for PCI Express... gt cpm integration english https://docs.amd.com/r/en-US/ug994-vivado-ip-subsystems/Parameter-Mismatch-Example Parameter Mismatch Example - Parameter Mismatch Example - 2025.2 English - UG994 The following is an example of a parameter mismatch on the FREQ_HZ property of a clock pin. In this example, the frequency does not match between the S01_AXI... parameter mismatch example english https://docs.amd.com/r/2021.1-English/ug994-vivado-ip-subsystems/Creating-Ports?contentId=nt6FTuw5y7li2feEpMHNXQ Creating Ports - Creating Ports - 2021.1 English - UG994 To use the Create Port option, right-click and select Create Port, as shown in the following figure. This feature is used for connecting individual signals,... creating ports english https://docs.amd.com/r/2023.2-English/ug994-vivado-ip-subsystems/General-Usage General Usage - General Usage - 2023.2 English - UG994 VHDL Add the attribute to the architecture section as shown below. architecture arch_impl of my_module is ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE... general usage english https://docs.amd.com/r/2023.2-English/ug994-vivado-ip-subsystems/Addressing-for-Block-Designs?contentId=0SvsBktW_C_qvN7xQSFSmg Addressing for Block Designs - Addressing for Block Designs - 2023.2 English - UG994 addressing block designs english https://docs.amd.com/r/2021.1-English/ug994-vivado-ip-subsystems/Debugging-IP-Integrator-Designs Debugging IP Integrator Designs - Debugging IP Integrator Designs - 2021.1 English - UG994 In-system debugging lets you debug your design in real-time on your target hardware. This is an essential step in design completion. Invariably, one comes... debugging ip integrator designs english https://docs.amd.com/r/2023.2-English/ug994-vivado-ip-subsystems/List-of-Supported-X_-Attributes List of Supported X_ Attributes - List of Supported X_ Attributes - 2023.2 English - UG994 The following is a list of all attributes supported by the IP packager, Module Reference flow, and their components. X_INTERFACE_INFO Attach to: Port Syntax:... list of supported x attributes english https://docs.amd.com/r/2022.2-English/ug994-vivado-ip-subsystems/Debugging-IP-Integrator-Designs Debugging IP Integrator Designs - Debugging IP Integrator Designs - 2022.2 English - UG994 In-system debugging lets you debug your design in real-time on your target hardware. This is an essential step in design completion. Invariably, one comes... debugging ip integrator designs english https://docs.amd.com/r/2023.2-English/ug994-vivado-ip-subsystems/Versal-Designs-with-IP-Integrator?contentId=mP59a1XtnHut1hi1yTGFXg Versal Designs with IP Integrator - Versal Designs with IP Integrator - 2023.2 English - UG994 versal designs ip integrator english https://docs.amd.com/r/en-US/ug994-vivado-ip-subsystems/Address-Path-Property-View Address Path Property View - Address Path Property View - 2025.2 English - UG994 When you select an address path in the address editor, the properties window displays the Address Path Properties. Figure 1. Displaying the Address Path... property view address path english https://docs.amd.com/r/2023.2-English/ug994-vivado-ip-subsystems/Top-Down-Design-Flow Top Down Design Flow - Top Down Design Flow - 2023.2 English - UG994 In this flow, a diagram for the top-level block design is created first. The designer or a team lead then creates proper hierarchies in the top-level block... top down design flow english https://docs.amd.com/r/2022.2-English/ug994-vivado-ip-subsystems/Hierarchical-IP-in-IP-Integrator Hierarchical IP in IP Integrator - Hierarchical IP in IP Integrator - 2022.2 English - UG994 Some IP in the IP catalog are hierarchical, and offer a child BD inside the top-level BD to display the logical configuration of the IP. These hierarchical IP... hierarchical ip integrator english https://docs.amd.com/r/2023.1-English/ug994-vivado-ip-subsystems/Handling-Constraints-in-RTL-Modules Handling Constraints in RTL Modules - Handling Constraints in RTL Modules - 2023.1 English - UG994 Constraints are not automatically associated it with a module reference block. You need to add the appropriate constraints to the top-level project where the... handling constraints rtl modules english https://docs.amd.com/r/en-US/ug994-vivado-ip-subsystems/Resource-Estimation-in-Block-Design?contentId=CJM5hDnVLNz_jMsIUWPeZA Resource Estimation in Block Design - Resource Estimation in Block Design - 2025.2 English - UG994 You can get the real time resource utilization numbers in BD by enabling the option Resource Estimation from Project Settings as shown in the following figure.... block design resource estimation english https://docs.amd.com/r/2022.2-English/ug994-vivado-ip-subsystems/Addressing-Overview Addressing Overview - Addressing Overview - 2022.2 English - UG994 Masters such as a processor need to access slaves such as peripherals and memory. Masters access slaves by reading and writing to specific addresses over an... addressing overview english https://docs.amd.com/r/2022.2-English/ug994-vivado-ip-subsystems/Parameter-Propagation Parameter Propagation - Parameter Propagation - 2022.2 English - UG994 In IP integrator, parameter propagation takes place when you choose to run Validate Design. You can do this in one of the following ways: Click Validate Design... parameter propagation english https://docs.amd.com/r/en-US/ug994-vivado-ip-subsystems/Creating-Hierarchies?contentId=HgfPjT2T4UsBhablQ9z_Jw Creating Hierarchies - Creating Hierarchies - 2025.2 English - UG994 You can create a hierarchical block in a diagram by using Ctrl+Click to select the desired IP blocks, right-click and select Create Hierarchy, as shown in the... creating hierarchies english https://docs.amd.com/r/2020.2-English/ug994-vivado-ip-subsystems/Show-in-Browser Show in Browser - Show in Browser - 2020.2 English - UG994 The toolbar button next to the scale allows the address map to be shown in a web browser. The address map is still fully interactive in the browser. If the... show browser english https://docs.amd.com/r/2021.2-English/ug994-vivado-ip-subsystems/Non-Project-Script Non-Project Script - Non-Project Script - 2021.2 English - UG994 The following is a sample script for creating a block design in non-project mode. #Set the target part, target language, and board part set_part... non project script english https://docs.amd.com/r/2023.2-English/ug994-vivado-ip-subsystems/Resource-Estimation-in-Block-Design?contentId=yOWOyS2ACJn57oZWAr_bYg Resource Estimation in Block Design - Resource Estimation in Block Design - 2023.2 English - UG994 You can get the real time resource utilization numbers in BD by enabling the option Resource Estimation from Project Settings as shown in the following figure.... block design resource estimation english https://docs.amd.com/r/2021.2-English/ug994-vivado-ip-subsystems/Scale-and-Zoom Scale and Zoom - Scale and Zoom - 2021.2 English - UG994 Slaves can be shown using three scale options: log, linear, and constant size. Figure 1. Scale Options The default is a log scale, where the vertical size of... scale zoom english https://docs.amd.com/r/2023.2-English/ug994-vivado-ip-subsystems/Parameter-Propagation?contentId=JR9_rhBDJl9Uq0SoJ~fvDw Parameter Propagation - Parameter Propagation - 2023.2 English - UG994 In IP integrator, parameter propagation takes place when you choose to run Validate Design. You can do this in one of the following ways: Click Validate Design... parameter propagation english https://docs.amd.com/r/2023.1-English/ug994-vivado-ip-subsystems/NoC-IP-DDR4-Memory-Controllers NoC IP DDR4 Memory Controllers - NoC IP DDR4 Memory Controllers - 2023.1 English - UG994 The DDR4 memory controllers (DDRMCs) are integrated into the axi_noc IP. The IP customization in the Vivado IP integrator also allows connecting memory... memory controllers noc ip english https://docs.amd.com/r/2023.2-English/ug994-vivado-ip-subsystems/Editor-Columns?contentId=aEZQg3CPgpLgLJT_Tg2Llw Editor Columns - Editor Columns - 2023.2 English - UG994 The address editor columns can be shown and hidden by right-clicking on the column header. The name column for parent rows gives the name of the object... editor columns english https://docs.amd.com/r/2021.2-English/ug994-vivado-ip-subsystems/Connecting-Interface-Signals?contentId=eE90FV1Xcmf3EqqJHGVtDQ Connecting Interface Signals - Connecting Interface Signals - 2021.2 English - UG994 To connect to the individual signals or buses that are part of an interface pin, you can expand the interface pin to display those individual signals. Clicking... connecting interface signals english https://docs.amd.com/r/2021.1-English/ug994-vivado-ip-subsystems/Making-Ports-External?contentId=TLPWKASkbT3kKiP0LFs5qg Making Ports External - Making Ports External - 2021.1 English - UG994 To connect signals or interfaces to external ports on a diagram, first select a pin, bus, or interface connection, as shown in the following figure.... making ports external english https://docs.amd.com/r/2023.2-English/ug994-vivado-ip-subsystems/Apertures?contentId=O2EUP_JlT~d5xJpRELF7mw Apertures - Apertures - 2023.2 English - UG994 Apertures are important in address assignment. As stated in the terminology section, an aperture is an offset and range that restricts where a slave segment... apertures english https://docs.amd.com/r/2023.2-English/ug994-vivado-ip-subsystems/Creating-Hierarchies Creating Hierarchies - Creating Hierarchies - 2023.2 English - UG994 You can create a hierarchical block in a diagram by using Ctrl+Click to select the desired IP blocks, right-click and select Create Hierarchy, as shown in the... creating hierarchies english https://docs.amd.com/r/2023.2-English/ug994-vivado-ip-subsystems/Slice Slice - Slice - 2023.2 English - UG994 To rip bits out of a bus signal, use the Slice IP. The Din Width field specifies the width of the input bus, and Din From and Din Down To fields specify the... slice english https://docs.amd.com/r/en-US/ug994-vivado-ip-subsystems/Utility-Vector-Logic?contentId=gL76GDEiac4BfPU6xaxgbg Utility Vector Logic - Utility Vector Logic - 2025.2 English - UG994 This IP can be configured for different logic modes and input widths. The supported logic operations are AND, OR, XOR, and NOT. The C_Size is the vector size... utility vector logic english https://docs.amd.com/r/2021.1-English/ug994-vivado-ip-subsystems/Block-Diagram-Addressing-View?contentId=MGqTlD5IewUBva~pTYZzCQ Block Diagram Addressing View - Block Diagram Addressing View - 2021.1 English - UG994 Vivado IP integrator provides a pre-built preset to show addressing view of the block design canvas. When you select this view, only the addressing... block diagram addressing view english https://docs.amd.com/r/en-US/ug994-vivado-ip-subsystems/IP-Instances-or-Block-Design-Cells IP Instances or Block Design Cells - IP Instances or Block Design Cells - 2025.2 English - UG994 IP instances or cells on the BD are in-memory objects. That is a copy of the instantiated IP is created in memory, but it is not written to disk until you save... block design ip instances cells english https://docs.amd.com/r/2021.2-English/ug994-vivado-ip-subsystems/Creating-Interface-Ports?contentId=Pl3_waXAjKAV6W_NNu4Cvg Creating Interface Ports - Creating Interface Ports - 2021.2 English - UG994 To use the create interface port option: Right-click and select Create Interface Port, as shown in the following figure. This command creates ports on the... creating interface ports english https://docs.amd.com/r/2021.2-English/ug994-vivado-ip-subsystems/Finding-Objects-in-a-Block-Design?contentId=j7xIxPZl0soO1kX2AkHsTg Finding Objects in a Block Design - Finding Objects in a Block Design - 2021.2 English - UG994 There are two ways of finding objects in a block design. The first one is used in the block design canvas. This functionality can be invoked by clicking the... in a block design finding objects english https://docs.amd.com/r/2023.1-English/ug994-vivado-ip-subsystems/Examining-Generated-Output-Products?contentId=Uig5~ufZ3hpwq9ivR78gUw Examining Generated Output Products - Examining Generated Output Products - 2023.1 English - UG994 output products examining generated english https://docs.amd.com/r/2023.2-English/ug994-vivado-ip-subsystems/Generating-Output-Products?contentId=WQzUTEAI_1Lhl14lfxoa4A Generating Output Products - Generating Output Products - 2023.2 English - UG994 You can Generate Output Products as follows: In the Flow Navigator, click Generate Block Design. Alternatively, you can highlight the block design in the... output products generating english https://docs.amd.com/r/2021.1-English/ug994-vivado-ip-subsystems/Exporting-Platforms-to-Vitis Exporting Platforms to Vitis - Exporting Platforms to Vitis - 2021.1 English - UG994 To start software development, user can export the hardware definition (XSA) to software environment after generating the design. This exports the necessary... exporting platforms vitis english https://docs.amd.com/r/2022.1-English/ug994-vivado-ip-subsystems/Interface-Type-Settings Interface Type Settings - Interface Type Settings - 2022.1 English - UG994 AXI Port There must be at least one enabled AXI port master interface within the platform. Once enabled, AXI port interfaces have the following settings:... interface type settings english https://docs.amd.com/r/2023.2-English/ug994-vivado-ip-subsystems/Creating-a-Block-Design?contentId=WrOUdohEygfc4stxt0MPoA Creating a Block Design - Creating a Block Design - 2023.2 English - UG994 You can create a block design (BD) inside the current project directory, or outside of the project directory structure. A common use case for creating the BD... a block creating design english https://docs.amd.com/r/2022.1-English/ug994-vivado-ip-subsystems/Pinning-Blocks-and-Ports-to-Location?contentId=Oemv6gRekXNjqF8j2h0tZw Pinning Blocks and Ports to Location - Pinning Blocks and Ports to Location - 2022.1 English - UG994 Often times cells in block designs need to arranged in a specific way to show control or data paths of a design. The pinning function in IP integrator provides... pinning blocks ports location english https://docs.amd.com/r/2022.2-English/ug994-vivado-ip-subsystems/Finding-Objects-in-a-Block-Design Finding Objects in a Block Design - Finding Objects in a Block Design - 2022.2 English - UG994 There are two ways of finding objects in a block design. The first one is used in the block design canvas. This functionality can be invoked by clicking the... in a block design finding objects english https://docs.amd.com/r/2022.1-English/ug994-vivado-ip-subsystems/Solution-Centers?contentId=OuQ~sSuG3RxlTl~51z5IoQ Solution Centers - Solution Centers - 2022.1 English - UG994 See the Xilinx Solution Centers for support on devices, software tools, and intellectual property at all stages of the design cycle. Topics include design... solution centers english https://docs.amd.com/r/en-US/ug994-vivado-ip-subsystems/External-Connections?contentId=VbWaEnHEQVfnReQWw3JgWQ External Connections - External Connections - 2025.2 English - UG994 You can connect signals and interfaces to external I/O ports as follows: Making Ports External Creating Ports Creating Interface Ports The following sections... external connections english https://docs.amd.com/r/2020.2-English/ug994-vivado-ip-subsystems/Working-with-Block-Designs Working with Block Designs - Working with Block Designs - 2020.2 English - UG994 At this point, you should know how to create a block design (BD), populate it with IP, make connections, assign memory address spaces, and validate the design.... working with block designs english https://docs.amd.com/r/2021.1-English/ug994-vivado-ip-subsystems/Masters Masters - Masters - 2021.1 English - UG994 The Masters section on the left of the Slaves shows the masters grouped by BD cells. Each BD cell has a set of master interfaces, represented by vertical... masters english https://docs.amd.com/r/2020.2-English/ug994-vivado-ip-subsystems/Creating-a-Project Creating a Project - Creating a Project - 2020.2 English - UG994 You can create entire designs using IP integrator; however, the typical design consists of HDL, IP, and IP integrator block designs (BDs). This section is an... creating a project english