Robuta

Sponsor of the Day: Jerkmate

https://blog.vmsplice.net/2026/01/building-virtio-serial-fpga-device-part_01619779257.html Stefan Hajnoczi: Building a virtio-serial FPGA device (Part 2): MMIO registers, DMA, and interrupts This is the second post in a series about building a virtio-serial device in Verilog for an FPGA development board. This time we stefan hajnoczi building virtio serial fpga device part 2 registers https://gitlab.com/stefanha/virtio-serial-fpga Stefan Hajnoczi / virtio-serial-fpga · GitLab virtio serial fpga stefan hajnoczi gitlab https://blog.vmsplice.net/2026/01/building-virtio-serial-fpga-device-part_01938158793.html Stefan Hajnoczi: Building a virtio-serial FPGA device (Part 3): virtio-serial device design This is the third post in a series about building a virtio-serial device in Verilog for an FPGA development board. This time we stefan hajnoczi building virtio serial fpga part 3 design device https://gitlab.com/stefanha/virtio-serial-fpga-picorv32/-/blob/main/picosoc/uart_reader.v picosoc/uart_reader.v · main · Stefan Hajnoczi / virtio-serial-fpga-picorv32 · GitLab virtio serial fpga stefan hajnoczi uart reader main https://blog.vmsplice.net/2026/01/building-virtio-serial-fpga-device-part_01060935865.html Stefan Hajnoczi: Building a virtio-serial FPGA device (Part 4): Virtqueue processing This is the fourth post in a series about building a virtio-serial device in Verilog for an FPGA development board. This time we stefan hajnoczi building virtio serial fpga device part 4 processing https://blog.vmsplice.net/2026/01/building-virtio-serial-fpga-device-part.html Stefan Hajnoczi: Building a virtio-serial FPGA device (Part 1): Overview This is a the first post in a series about building a virtio-serial device in Verilog for a Field Programmable Gate Array (FPGA) developme... stefan hajnoczi building virtio serial fpga device part 1 overview https://blog.vmsplice.net/2026/01/building-virtio-serial-fpga-device-part_01486670629.html Stefan Hajnoczi: Building a virtio-serial FPGA device (Part 6): Writing the RISC-V firmware This is the final post in a series about building a virtio-serial device in Verilog for an FPGA development board. This time we stefan hajnoczi building virtio serial fpga device part 6 writing risc